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automotive power data sheet rev. 1.1, 2014-10-23 TLE9260QXV33 mid-range system basis chip family body system ic with int egrated voltage regulators, power management functions, hs-can transceiver supporting can fd . featuring multiple high-side swit ches and high-voltage wake inputs. system basis chip
data sheet 2 rev. 1.1, 2014-10-23 TLE9260QXV33 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 hints for unused pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4 hints for alternate pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.4 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 system features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 block description of state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.1 device configuration and sbc init mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.1.1 device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.1.2 sbc init mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.2 sbc normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1.3 sbc stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1.4 sbc sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1.5 sbc restart mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1.6 sbc fail-safe mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.7 sbc development mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2 wake features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.1 cyclic sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.1.1 configuration and operation of cyclic sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.1.2 cyclic sense in low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.2.2 cyclic wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2.3 internal timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.3 supervision features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6 voltage regulator 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.1 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7 voltage regulator 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.1 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.2.1 short to battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8 high-side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.1 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.2.1 over and under voltage switch off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.2.2 over current detection and switch off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.2.3 open load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.2.4 hsx operation in different sbc modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table of contents
TLE9260QXV33 table of contents data sheet 3 rev. 1.1, 2014-10-23 8.2.5 pwm and timer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9 high speed can transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.1 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.2.1 can off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.2.2 can normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.2.3 can receive only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.2.4 can wake capable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.2.5 txd time-out feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.2.6 bus dominant clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.2.7 under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10 wake and voltage monitoring inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.1 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.2.1 wake input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.2.2 alternate measurement function with wk1 and wk2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.2.2.1 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.2.2.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 11 interrupt function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11.1 block and functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12 fail outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12.1 block and functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12.1.1 general purpose i/o functionality of fo2 and fo3 as al ternate function . . . . . . . . . . . . . . . . . . 74 12.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 13 supervision functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 13.1 reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 13.1.1 reset output description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 13.1.2 soft reset description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 13.2 watchdog function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 13.2.1 time-out watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 13.2.2 window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.2.3 watchdog setting check sum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.2.4 watchdog during sbc stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 13.2.5 watchdog start in sbc stop mode due to bus wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 13.3 vs power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 13.4 under voltage vs and vshs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13.5 over voltage vshs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13.6 vcc1 over-/ under voltage and under voltage prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13.6.1 vcc1 under voltage and under voltage prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13.6.2 vcc1 over voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 13.7 vcc1 short circuit diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 13.8 vcc2 undervoltage and vcan undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 13.9 thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 13.9.1 individual thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 13.9.2 temperature prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
TLE9260QXV33 table of contents data sheet 4 rev. 1.1, 2014-10-23 13.9.3 sbc thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 13.10 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14 serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 14.1 spi block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 14.2 failure signalization in the spi data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 14.3 spi programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 14.4 spi bit mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.5 spi control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 14.5.1 general control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 14.6 spi status information registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 14.6.1 general status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 14.6.2 family and product information register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 14.7 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 15 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 15.1 application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 15.2 esd tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 15.3 thermal behavior of package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 16 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 39 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
pg-vqfn-48-31 type package marking TLE9260QXV33 pg-vqfn-48-31 TLE9260QXV33 data sheet 5 rev. 1.1, 2014-10-23 mid-range system basis chip family TLE9260QXV33 1overview scalable system basis chip family ? product family with various products for complete scalable application coverage. ? dedicated data sheets are available for the different product variants ? complete compatibility (hardware and software ) across the family ? tle9263 with 2 lin transceivers, 3 voltage regulators ? tle9262 with 1 lin transceiver, 3 voltage regulators ? tle9261 without lin transceivers, 3 voltage regulators ? tle9260 without lin transceivers, 2 voltage regulators ? product variants for 5v (tle926xqx) and 3.3v (tle 926xqxv33) output voltage for main voltage regulator ? can partial networking variants for 5v (tle926x -3qx) and 3.3v (tle926x-3qxv33) output voltage device description the TLE9260QXV33 is a monolithic integrated circuit in an exposed pad vqfn-48 (7mm x 7mm) power package with lead tip inspection (lti) feature to support automatic optical inspection (aoi). the device is designed for various can automotive applic ations as main supply for the microcontroller and as interface for a can bus network. to support these applications, the system basis chip ( sbc) provides the main functions, such as a 3.3v low- dropout voltage regulator (ldo) for e.g. a microcontrolle r supply, another 5v low-dropout voltage regulator with off-board protection for e.g. sensor su pply , a hs-can transceiver supporting can fd for data transmission, high- side switches with embedded protective functions and a 16 -bit serial peripheral in terface (spi) to control and monitor the device. also implemented are a configurable timeout / window watchdog circuit with a reset feature, three fail outputs and an under voltage reset feature. the device offers low-power modes in order to minimize current consumption on applications that are connected permanently to the battery. a wake-up from the low-powe r mode is possible via a message on the buses, via the bi-level sensitive monitoring/wake-up inputs as well as via cyclic wake. the device is designed to withstand the seve re conditions of automotive applications.
TLE9260QXV33 overview data sheet 6 rev. 1.1, 2014-10-23 key features ? very low quiescent current cons umption in stop- and sleep mode ? periodic cyclic wake in sbc normal- and stop mode ? periodic cyclic sense in sbc normal-, stop- and sleep mode ? low-drop voltage regulator 3.3v, 250ma ? low-drop voltage regulator 5v, 100ma, pr otected features for off-board usage ? high-speed can transceiver: ? fully compliant to iso11898-2 and iso11898-5 ? suitable for chokeless operation up to 500kbps ? supporting can fd communication up to 2 mbps ? fully compliant to ?hardware requir ements for lin, can and flexray inte rfaces in automotive applications? revision 1.3, 2012-05-04 ? four high-side outputs 7 ? typ. ? dedicated supply pin for high-side outputs ? two general purpose high-voltage in- and outputs (gp ios) configurable as add. fa il outputs, wake inputs, low-side switches or high-side switches ? three universal high-voltage wake inputs for voltage level monitoring ? alternate high-voltage measurement func tion, e.g. for batt ery voltage sensing ? configurable wake-up sources ? reset output ? configurable timeout and window watchdog ? up to three fail outputs (depending on configuration) ? over temperature and short circuit protection feature ? wide supply input voltage and temperature range ? software compatible to all sbc families tle926x and tle927x ? green product (rohs co mpliant) & aec qualified ? pg-vqfn-48 leadless exposed-pad power package wit h lead tip inspection (l ti) feature to support automatic optical inspection (aoi)
TLE9260QXV33 block diagram data sheet 7 rev. 1.1, 2014-10-23 2 block diagram figure 1 block diagram v cc1 spi interrupt control sbc state machine sdi sdo clk csn vcc1 can cell window watchdog wk txdcan rxdcan vcan canh canl wk1 reset generator int gnd wake register vs v s fail safe ro fo 3/test fo2 fo1 v cc2 vcc2 high side hs2 hs3 hs4 hs1 wk wk2 wk wk3 vshs vs alter native function for fo 2/ 3: gpio 1/2 alternative function for w k 1 /2: voltage measur ement
TLE9260QXV33 pin configuration data sheet 8 rev. 1.1, 2014-10-23 3 pin configuration 3.1 pin assignment figure 2 pin configuration tle9260 pg-vqfn-48 tle9260.vsd 1 gnd 2 n. c. 3 n. u. 4 n. u. 5 n. u. 6 n. c. 7 n. c. 8 hs1 9 hs2 10 hs3 11 hs4 12 n. c. fo3/test 48 fo2 47 n.c. 46 n.c. 45 n.u. 44 gnd 43 n.u. 42 n.c. 41 canh 40 canl 39 gnd 38 vcan 37 13 vshs 14 vs 15 vs 16 n. c. 17 vcc1 18 vcc2 19 n. c. 20 gnd 21 fo1 22 wk1 23 wk2 24 wk3 25 n. u. 26 n. u. 27 clk 28 sdi 29 sdo 30 csn 31 int 32 ro 33 n. u. 34 n. u. 35 txdcan 36 rxdcan
TLE9260QXV33 pin configuration data sheet 9 rev. 1.1, 2014-10-23 3.2 pin definitions and functions pin symbol function 1gnd ground 2n.c. not connected; internally not bonded. 3n.u. not used; used for internal testing purpose. do not connect, leave open 4n.u. not used; used for internal testing purpose. do not connect, leave open 5n.u. not used; used for internal testing purpose. do not connect, leave open 6n.c. not connected; internally not bonded. 7n.c. not connected; internally not bonded. 8hs1 high side output 1; typ. 7 ? 9hs2 high side output 2; typ. 7 ? 10 hs3 high side output 3; typ. 7 ? 11 hs4 high side output 4; typ. 7 ? 12 n.c not connected; internally not bonded. 13 vshs supply voltage hs and gpio1/2 in hs configuration; supply voltage for high- side switches modules and respective uv-/ov supervision; connected to battery voltage with reverse protection diode and filter against emc ; connect to vs if separate supply is not needed 14 vs supply voltage; supply voltage for chip internal supply and voltage regulators; connected to battery voltage with external reverse protection diode and filter against emc 15 vs supply voltage; supply voltage for chip internal supply and voltage regulators; connected to battery voltage with external reverse protection diode and filter against emc 16 n.c. not connected; internally not bonded. 17 vcc1 voltage regulator output 1 18 vcc2 voltage regulator output 2 19 n.c. not connected; internally not bonded. 20 gnd gnd 21 fo1 fail output 1 22 wk1 wake input 1; alternative function: hv-mea surement function input pin (only in combination with wk2, see chapter 10.2.2 ) 23 wk2 wake input 2; alternative function: hv-measu rement function output pin (only in combination with wk1, see chapter 10.2.2 ) 24 wk3 wake input 3 25 n.u. not used; used for internal testing purpose. do not connect, leave open 26 n.u. not used; used for internal testing purpose. do not connect, leave open 27 clk spi clock input 28 sdi spi data input; into sbc (=mosi) 29 sdo spi data output; out of sbc (=miso) 30 csn spi chip select not input
TLE9260QXV33 pin configuration data sheet 10 rev. 1.1, 2014-10-23 note: all vs pins must be connected to battery potentia l or insert a reverse polarity diodes where required; all gnd pins as well as the cooling tab must be connected to one common gnd potential; 31 int interrupt output ; used as wake-up flag for microcontroller in sbc stop or normal mode and for indicating failures. active low. during start-up used to set the sbc configurat ion. external pull-up sets config 1/3, no external pull-up sets config 2/4. 32 ro reset output 33 n.u. not used; used for internal testing purpose. do not connect, leave open 34 n.u. not used; used for internal testing purpose. do not connect, leave open 35 txdcan transmit can 36 rxdcan receive can 37 vcan supply input; for internal hs-can cell 38 gnd gnd 39 canl can low bus pin 40 canh can high bus pin 41 n.c. not connected; internally not bonded. 42 n.u. not used; used for internal testing purpose. do not connect, leave open 43 gnd ground 44 n.u. not used; used for internal testing purpose. do not connect, leave open 45 n.c. not connected; internally not bonded. 46 n.c. not connected; internally not bonded. 47 fo2 fail output 2 - side indicator; side indicators 1.25hz 50% duty cycle output; open drain. active low. alternative function: gpio1 ; configurable pin as wk, or ls, or hs supplied by vshs (default is fo2, see also chapter 12.1.1 ) 48 fo3/test fail output 3 - pulsed light output; break/rear light 100hz 20% duty cycle output; open drain. active low test ; connect to gnd to activate sbc software de velopment mode; integrated pull-up resistor. connect to vs with pull-up resistor or leave open for normal operation. alternative function: gpio2 ; configurable pin as wk, or ls, or hs supplied by vshs (default is fo3, see also chapter 12.1.1 ) cooling tab gnd cooling tab - exposed die pad; for cooling purposes only, do not use as an electrical ground. 1) 1) the exposed die pad at the bottom of th e package allows better power dissipation of heat from the sbc via the pcb. the exposed die pad is not connected to any active part of the ic an can be left fl oating or it can be connected to gnd (recommended) for the best emc performance. pin symbol function
TLE9260QXV33 pin configuration data sheet 11 rev. 1.1, 2014-10-23 3.3 hints for unused pins it must be ensured that the correct c onfigurations are also selected, i.e. in case functions are not used that they are disabled via spi: ? wk1/2/3: connect to gnd and disable wk inputs via spi ? hsx: leave open ? canh/l, rxdcan, txdcan: leave all pins open ? ro / fox: leave open ? int: leave open ? test: connect to gnd during power-up to activate sbc development mode; connect to vs or leave open for normal user mode operation ? vcc2: leave open and keep disabled ? vcan: connect to vcc1 ? n.c.: not connected; internal ly not bonded; connect to gnd ? n.u. : not used; used for internal testin g purposes only. do not connect, leave open, i.e. not connected to any potential on the board. in case n.u. pins are connected on the board an open bridge has to be foreseen to avoid external disturbances. the bridge can be shorted by a 0 ? resistance if signal is needed. 3.4 hints for alternate pin functions in case of alternate pin functions, selectable via spi, it must be ensured that the correct configurations are also selected via spi, in case it is not done automatically. plea se consult the respective c hapter. in addition, following topics shall be considered: ? wk1..2: the pins can be either used as hv wake / voltage monitoring inputs or for a voltage measurement function (via bit wk_meas ). in the second case, the wk1..2 pins shall not be used / assigned for any wake detection nor cyclic sense functionality, i.e. wk1 and wk2 must be disabled in the register wk_ctrl_2 and the level informati on is to be ignored in the register wk_lvl_stat . ? fo2..3: the pins can also be configured as gpios in the gpio_ctrl register. in this case, the pins shall not be used for any fail output functionality. the defa ult function after power on reset (por) is fox.
TLE9260QXV33 general product characteristics data sheet 12 rev. 1.1, 2014-10-23 4 general product characteristics 4.1 absolute maximum ratings table 1 absolute maximum ratings 1) t j = -40 c to +150 c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. voltages supply voltage (vs, vshs) vs x, max -0.3 ? 28 v ? p_4.1.1 supply voltage (vs, vshs) vs x, max -0.3 ? 40 v load dump, max. 400 ms p_4.1.2 voltage regulator 1 v cc1, max -0.3 ? 5.5 v ? p_4.1.3 voltage regulator 2 v cc2, max -0.3 ? 28 v v cc2 = 40v for load dump, max. 400 ms; p_4.1.4 wake inputs wk1..3 v wk, max -0.3 ? 40 v ? p_4.1.6 fail pin fo1 v fo1, max -0.3 ? 40 v ? p_4.1.7 fail pins fo2, fo3/test v fo2_3, max -0.3 ? v s + 0.3 v ? p_4.1.23 canh, canl v bus, max -27 ? 40 v ? p_4.1.8 logic input pins (csn, clk, sdi, txdcan) v i, max -0.3 ? v cc1 + 0.3 v ? p_4.1.9 logic output pins (sdo, ro, int, rxdcan) v o, max -0.3 ? v cc1 + 0.3 v ? p_4.1.10 vcan input voltage v vcan, max -0.3 ? 5.5 v ? p_4.1.11 high side 1...4 v hs, max -0.3 ? v shs + 0.3 v ? p_4.1.12 currents wake input wk1 i wk1,max 0?500a 2) p_4.1.13 wake input wk2 i wk2,max -500 ? 0 a 2) p_4.1.14 temperatures junction temperature t j -40 ? 150 c ? p_4.1.15 storage temperature t stg -55 ? 150 c ? p_4.1.16 esd susceptibility esd resistivity v esd,11 -2 ? 2 kv hbm 3) p_4.1.17 esd resistivity to gnd, hsx v esd,12 -2 ? 2 kv hbm 3) p_4.1.18 esd resistivity to gnd, canh, canl v esd,13 -8 ? 8 kv hbm 4)3) p_4.1.19
TLE9260QXV33 general product characteristics data sheet 13 rev. 1.1, 2014-10-23 notes 1. stresses above the ones listed here may cause perma nent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. integrated protection func tions are designed to prevent ic destructi on under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. pr otection functi ons are not designed for continuous repetitive operation. esd resistivity to gnd v esd,21 -500 ? 500 v cdm 5) p_4.1.20 esd resistivity pin 1, 12,13,24,25,36,37,48 (corner pins) to gnd v esd,22 -750 ? 750 v cdm 5) p_4.1.21 1) not subject to production test, specified by design. 2) applies only if wk1 and wk2 are configur ed as alternative hv-measurement function 3) esd susceptibility, hb m according to ansi/esd a/jedec js-001 (1.5 k ? , 100 pf) 4) for esd ?gun? resistivity 6kv (according to iec61000-4-2 ?gun test? (150pf, 330 ? )), will be shown in application information and test report will be provided from ibee 5) esd susceptibility, charged device model ?cdm? eia/jesd22-c101 or esda stm5.3.1 table 1 absolute maximum ratings 1) (cont?d) t j = -40 c to +150 c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
TLE9260QXV33 general product characteristics data sheet 14 rev. 1.1, 2014-10-23 4.2 functional range note: within the functional range the ic operates as de scribed in the circuit description. the electrical characteristics are specifi ed within the conditions given in the re lated electrical ch aracteristics table. device behavior outside of specified functional range: ?28v < v s,func < 40v: device will still be functional including the state machine; the specified electrical characteristics might not be ensur ed anymore. the regulators vcc1/2/3 are working properly, however, a thermal shutdown might occur due to high power diss ipation. hsx switches migh t be turned off depending on vshs_ov configurations. the specified spi commu nication speed is ensured; the absolute maximum ratings are not violated, however the device is not intended for continu ous operation of vs >28v. the device operation at high junction temperatures for lo ng periods might reduce the operating life time; ? v can < 4.75v: the undervoltage bit vcan_uv will be set in th e spi register bus_stat_1 and the transmitter will be disabled as long as the uv condition is present; ?5.25v < v can < 5.50v: can transceiver still functional. however, the communi cation might fail due to out-of- spec operation; ? v por,f < vs < 5.5v: device will still be functional; the specif ied electrical characterist ics might not be ensured anymore. ? the voltage regulators will en ter the lo w-drop oper ation mode, ? a vcc1_uv reset could be triggered depending on the vrtx settings, ? hsx switch behavior will depend on the respective configuration: - hs_uv_sd_en = ?0? (default): hsx will be turned off for vshs < vshs_uv and will stay off; - hs_uv_sd_en = ?1?: hsx stays on as long as possible. an unwanted over current shut down may occur. oc shut down bit set and the resp ective hsx switch will stay off; ? fox outputs will remain on if they were enabled before vs > 5.5v, ? the specified spi communication speed is ensured. table 2 functional range parameter symbol values unit note / test condition number min. typ. max. supply voltage v s,func v por ?28v 1) v por see section chapter 13.10 1) including power-on reset, over- and under voltage protection p_4.2.1 can supply voltage v can,func 4.75 ? 5.25 v ? p_4.2.3 spi frequency f spi ??4mhzsee chapter 14.7 for f spi,max p_4.2.4 junction temperature t j -40 ? 150 c ? p_4.2.5
TLE9260QXV33 general product characteristics data sheet 15 rev. 1.1, 2014-10-23 4.3 thermal resistance table 3 thermal resistance 1) 1) not subject to production test, specified by design. parameter symbol values unit note / test condition number min. typ. max. junction to soldering point r thjsp ? 6 ? k/w exposed pad p_4.3.1 junction to ambient r thja ?33?k/w 2) 2) according to jedec jesd51-2,-5,-7 at natural convection on fr4 2s2p board for 1.5w. board: 76.2x114.3x1.5mm3 with 2 inner copper layers (35m thick), with thermal via array under the exposed pad contacting t he first inner copper layer and 300mm2 cooling area on t he bottom layer (70m). p_4.3.2
TLE9260QXV33 general product characteristics data sheet 16 rev. 1.1, 2014-10-23 4.4 current consumption table 4 current consumption current consumption values are specified at tj = 25c, vs = 13.5v, all outputs open (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. sbc normal mode normal mode current consumption i normal ?3.56.5ma v s = 5.5 v to 28 v; t j = -40 c to +150 c; vcc2, can, hsx = off p_4.4.1 sbc stop mode stop mode current consumption i stop_1,25 ?4460a 1) vcc2, hsx = off; can, wkx not wake capable; watchdog = off; no load on vcc1; i_peak_th = ?0? p_4.4.2 stop mode current consumption i stop_1,85 ?5070a 1)2) t j = 85c; vcc2, hsx = off; can, wkx not wake capable; watchdog = off; no load on vcc1; i_peak_th = ?0? p_4.4.3 stop mode current consumption (high active peak threshold) i stop_2,25 ?6490a 1) vcc2, hsx = off; can, wkx not wake capable; watchdog = off; no load on vcc1; i_peak_th = ?1? p_4.4.35 stop mode current consumption (high active peak threshold) i stop_2,85 ? 70 100 a 1)2) tj = 85c; vcc2, hsx = off; can, wkx not wake capable; watchdog = off; no load on vcc1; i_peak_th = ?1? p_4.4.36 sbc sleep mode sleep mode current consumption i sleep,25 ? 15 25 a vcc2, hsx = off; can, wkx not wake capable p_4.4.5 sleep mode current consumption i sleep,85 ?2535a 2) t j = 85c; vcc2, hsx = off; can, wkx not wake capable p_4.4.6
TLE9260QXV33 general product characteristics data sheet 17 rev. 1.1, 2014-10-23 feature incremental current consumption current consumption for can module, recessive state i can,rec ? 2 3 ma sbc normal/stop mode; can normal mode; vcc1 connected to vcan; vtxdcan = vcc1; no rl on can p_4.4.7 current consumption for can module, dominant state i can,dom ?34.5ma 2) sbc normal/stop mode; can normal mode; vcc1 connected to vcan; vtxdcan = gnd; no rl on can p_4.4.8 current consumption for can module, receive only mode i can,rcvonly ?0.91.2ma 2) sbc normal/stop mode; can receive only mode; vcc1 connected to vcan; vtxdcan = vcc1; no rl on can p_4.4.9 current consumption for wk1..3 wake capability (all wake inputs) i wake,wkx,25 ?0.22a 3)4)5) sbc sleep mode; wk1..3 wake capable (all wkx enabled); can = off p_4.4.13 current consumption for wk1..3 wake capability (all wake inputs) i wake,wkx,85 ?0.53a 2)3)4)5) sbc sleep mode; t j = 85c; wk1..3 wake capable; (all wkx enabled); can = off p_4.4.14 current consumption for can wake capability i wake,can,25 ?4.56a 3) sbc sleep mode; can wake capable; wk1..3 p_4.4.17 current consumption for can wake capability i wake,can,85 ?5.57a 2)3) sbc sleep mode; t j = 85c; can wake capable; wk1..3 p_4.4.18 vcc2 normal mode current consumption i normal,vcc2 ?2.53.5ma v s = 5.5 v to 28 v; t j = -40 c to +150 c; vcc2 = on (no load) p_4.4.32 current consumption for vcc2 in sbc sleep mode i sleep,vcc2,25 ?2535a 1)3) sbc sleep mode; vcc2 = on (no load); can, wk1..3 = off p_4.4.19 table 4 current consumption (cont?d) current consumption values are specified at tj = 25c, vs = 13.5v, all outputs open (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
TLE9260QXV33 general product characteristics data sheet 18 rev. 1.1, 2014-10-23 current consumption for vcc2 in sbc sleep mode i sleep,vcc2,85 ?3040a 1)2)3) sbc sleep mode; t j = 85c; vcc2 = on (no load); can, wk1..3 = off p_4.4.20 current consumption for hsx in sbc stop mode i stop,hsx,25 ? 525 650 a 3)6) sbc stop mode; cyclic sense & hsx= on (no load); can, wk1..3 = off p_4.4.33 current consumption for hsx in sbc stop mode i stop,hsx,85 ? 575 700 a 2)3)6) sbc stop mode; t j = 85c; cyclic sense & hsx = on (no load); can, wk1..3 = off p_4.4.34 current consumption for cyclic sense function i stop,cs25 ?2026a 3)7)8) sbc stop mode; wd = off p_4.4.23 current consumption for cyclic sense function i stop,cs85 ?2435a 2)3)7)8) sbc stop mode; t j = 85c; wd = off p_4.4.27 current consumption for watchdog active in stop mode i stop,wd25 ?2026a 2) sbc stop mode; watchdog running p_4.4.30 current consumption for watchdog active in stop mode i stop,wd85 ?2435a 2) sbc stop mode; t j = 85c; watchdog running p_4.4.31 current consumption for active fail outputs (fo1..3) i stop,fox ?1.02.0ma 2) all sbc modes; t j = 25c; fox = on (no load); p_4.4.24 1) if the load current on vcc1 will ex ceed the configured vcc1 active peak thre shold ivcc1,ipeak1,r or ivcc1,ipeak2,r, the current consumption will increase by typ. 2.9ma to ensure optimum dynamic load behavior. same applies to vcc2.. see also chapter 6 , chapter 7 . 2) not subject to production test, specified by design. 3) current consumption adders of features defined for sbc sleep mode also apply for sbc stop mode and vice versa (unless otherwise specified). 4) no pull-up or pull-down configuration selected. 5) the specified wkx current consumption adder for wake capabi lity applies regardless how many wk inputs are activated. 6) a typ. 75a / max 125a ( t j = 85c) adder applies for every additiona lly activated hsx switch in sbc stop mode; in sbc normal mode every hsx switch consumes the typ. 75a / max 125a ( t j = 85c) without the initial adder because the biasing is already enabled. 7) hs1 used for cyclic sense, timer 2, 20m s period, 0.1ms on-time, no load on hs1. in general the current consumption adder for cyclic sens e in sbc stop mode can be calculated with below equation: istop,cs = 18a + (525a *ton/tper) 8) also applies to cyclic wake table 4 current consumption (cont?d) current consumption values are specified at tj = 25c, vs = 13.5v, all outputs open (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
TLE9260QXV33 general product characteristics data sheet 19 rev. 1.1, 2014-10-23 note: there is no additional current consum ption contribution due to pwm generators.
TLE9260QXV33 system features data sheet 20 rev. 1.1, 2014-10-23 5 system features this chapter describes the system feat ures and behavior of the TLE9260QXV33: ? state machine ? sbc mode control ? device configuration ? state of supply and peripherals ? system functions such as cyclic sense or cyclic wake ? supervision and diagnosis functions the system basis chip (sbc) offers six operating modes: ? sbc init mode: power-up of t he device and after a soft reset, ? sbc normal mode: the main operating mode of the device, ? sbc stop mode: the first-level power saving m ode with the main voltage regulator vcc1 enabled, ? sbc sleep mode: the second-level power saving mode with vcc1 disabled, ? sbc restart mode: an intermediate mode after a wake event from sbc sleep or fail-safe mode or after a failure (e.g. wd failure, vcc1 under vo ltage reset) to bring the microcontrolle r into a defined state via a reset. once the failure condition is not present anymore th e device will automatically change to sbc normal mode after a delay time ( t rd1 ). ? sbc fail-safe mode: a safe-state mode after critical failures (e.g. wd failure, vcc1 under voltage reset) to bring the system into a safe state and to ensure a pr oper restart of the system. vcc1 is disabled. it is a permanent state until either a wake event (via can or wkx) occurs or the over temperature condition is not present anymore. a special mode, called sbc development mode, is availa ble during software development or debugging of the system. all above mentioned operating modes can be a ccessed in this mode. however, the watchdog counter is stopped and does not need to be triggered. this mode can be accessed by setting the test pin to gnd during sbc init mode. the device can be configured via hardware (external co mponent) to determine the device behavior after a watchdog trigger failure. see chapter 5.1.1 for further information. the system basis chip is controlled via a 16-bit sp i interface. a detailed description can be found in chapter 14 .the configuration as well as the diagnosis is handled via the spi. the spi mapping of the TLE9260QXV33 is compatible to other devices of the tl e926x and tle927x families.
TLE9260QXV33 system features data sheet 21 rev. 1.1, 2014-10-23 5.1 block description of state machine the different sbc modes are selected vi a spi by setting the respective sbc mode bits in the register m_s_ctrl . the sbc mode bits are cleared when going through sbc restart mode and thus always show the current sbc mode. figure 3 state diagram showing the sbc operating modes sbc init mode * (long open window) vcc1 on vcc2 off fox inact. can (3) off wake up event spi cmd spi cmd spi cmd any spi command wd trigger first battery connection vcc1 undervoltage automatic 1st watchdog failure config 2, 2nd watchdog failure, config 4 vcc1 short to gnd sbc soft reset reset is released wd starts with long open window (1) after fail-safe mode entry, the device will stay for at least typ . 1s in this mode (with ro low) after a tsd2 event and min. typ. 100ms after other fail-safe events. only then the device can leave the mode via a wake-up event. wake events are stored during this time. (3) for sbc development mode can /vcc2 are on in sbc init mode and stay on when going from there to sbc normal mode (4) see chapter can for detailed behavior in sbc restart mode (5) see chapter 5.1.5 and 12.1 for detailed fox behavior wd config. hsx off sbc normal mode vcc1 on vcc2 config. fox act/inact can (3) config. wd config. hsx config. sbc sleep mode vcc1 off vcc2 fixed fox fixed can wake capable /off wd off. hsx fixed sbc stop mode vcc1 on vcc2 fixed fox fixed can fixed wd fixed hsx fixed sbc restart mode (ro pin is asserted) vcc1 on/ ramping vcc2 off fox (5) active/ fixed can (4) woken / off wd off hsx off sbc fail-safe mode (1) vcc1 off vcc2 off fox (5) active can wake capable wd off hsx off config . : settings can be changed in this sbc mode ; fixed : settings stay as defined in sbc normal mode tsd2 event, * the sbc development mode is a super set of state machine where the wd timer is stopped and can behavior differs in sbc init mode . otherwise , there are no differences in behavior . cyc. wake off cyc. sense off cyc. wake config. cyc. sense config. cyc. wake fixed cyc. sense fixed cyc. wake off cyc. sense fixed cyc. wake off cyc. sense off cyc. wake off cyc. sense off can, wkx wake-up event or release of over temperature tsd2 after t ts d2 vcc1 over voltage config 2/4 (if vcc_ov_rst set) vcc1 over voltage config 1/3 (if vcc_ov_rst set) watchdog failure: config 1/3 & 1st wd failure in config 4 after 4x consecutive vcc 1 under voltage events (if vs > vs_uv)
TLE9260QXV33 system features data sheet 22 rev. 1.1, 2014-10-23 5.1.1 device configurat ion and sbc init mode the sbc starts up in sbc init mode after crossing the power-on reset v por,r threshold (see also chapter 13.3 ) and the watchdog will start with a long open window ( t lw ). during this power-on phase following configurations are stored in the device: ? the device behavior regarding a watchdog trigger failure and a vcc1 over voltage condition is determined by the external circuitry on the int pin (see below) ? the selection of the normal device operation or the sbc software development mode (watchdog disabled for debugging purpos es) will be set depending on the voltage level of the fo3/test pin (see also chapter 5.1.7 ). 5.1.1.1 device configuration the configuration selection is intended to select the sbc behavior regarding a watchdog trigger failure. depending on the requirements of the application, the vcc1 output shall be switched off and the device shall go to sbc fail-safe mode in case of a watchdog fa ilure (1 or 2 fails). to set this configuration (config 2/4), the int pin does not need an external pull-up resistor. in case vcc1 sh ould not be switched off (c onfig 1/3), the int pin needs to have an external pull-up resistor con nected to vcc1 (see application diagram in chapter 15.1 ). figure 5 shows the timing diagram of the hardware configur ation selection. the hardware configuration is defined during sbc init mode. the int pin is internally pulled low with a weak pull-down resistor during the reset delay time t rd1 , i.e.after vcc1 crosses the rese t threshold vrt1 and before the ro pin goes high. the int pin is monitored during this time (with a continuos filter time of t cfg_f ) and the configuration (depending on the voltage level at int) is stored at the rising edge of ro. note: if the por bit is not cleared then the internal pull-down re sistor will be reactivated every time ro is pulled low the configuration will be updated at the rising edge of ro. therefor e it is recommended to clear the por bit right after initialization. in ca se there is no stable signal at int, then the default value ?0? will taken as the config select va lue = sbc fail-safe mode. figure 4 hardware configuration selection timing diagram t vcc1 t ro t vs v por,r t rd1 v rt1,r t cfg_f configuration selection monitoring period continuous filtering with
TLE9260QXV33 system features data sheet 23 rev. 1.1, 2014-10-23 there are four different device configurations ( table 5 ) available defining the watchdog failure and the vcc1 over voltage behavior. the configurations can be selected via the external connection on the int pin and the spi bit cfg in the hw_ctrl register (see also chapter 14.4 ): ? cfgp = ?1?: config 1 and config 3: ? a watchdog trigger failure leads to sbc restart mode and depending on cfg the fail outputs (fox) are activated after the 1st (config 1) or 2nd (config 3) watchdog trigger failure; ? a vcc1 over voltage detection will lead to sbc re start mode if vcc1_ov_rst is set. vcc1_ ov will be set and the fail outputs are activated; ? cfgp = ?0?: config 2 and config 4: ? a watchdog trigger failure leads to sbc fail-safe mode and depending on cfg the fail outputs (fox) are activated after the 1st (config 2) or 2nd (config 4) wa tchdog trigger failure. the first watchdog trigger failure in config 4 will lead to sbc restart mode; ? a vcc1 over voltage detection will lead to sbc fail-safe mode if vcc1_ov_rst is set. vcc1_ ov will be set and the fail outputs are activated; the respective device configuration can be identified by reading the spi bit cfg in the hw_ctrl register and the cfgp bit in the wk_lvl_stat register. table 5 shows the configurations and the device behavior in case of a watchdog trigger failure: table 6 shows the configurations and the device behavior in case of a vcc1 over voltage detection when vcc1_ov_rst is set: the respective configur ation will be stored for all co nditions and can only be changed by powering down the device (vs < v por,f ). table 5 watchdog trigger failure configuration config int pin ( cfgp )spi bit cfg event fox activati on sbc mode entry 1 external pull-up 1 1 x watchdog failure after 1st wd failure sbc restart mode 2 no ext. pull-up 1 1 x watchdog failure after 1st wd failure sbc fail-safe mode 3 external pull-up 0 2 x watchdog failure after 2nd wd failure sbc restart mode 4 no ext. pull-up 0 2 x watchdog failure after 2nd wd failure sbc fail-safe mode table 6 device behavior in case of vcc1 over voltage detection config int pin ( cfgp ) cfg bit vcc1_o v_rst event vcc1 _ ov fox activation sbc mode entry 1-4 any value x 0 1 x vcc1 ov 1 no fox activation unchanged 1 external pull-up 1 1 1 x vcc1 ov 1 a fter 1st vcc1 ov sbc restart mode 2 no ext. pull-up 1 1 1 x vcc1 ov 1 after 1st vcc1 ov sbc fail-safe mode 3 external pull-up 0 1 1 x vcc1 ov 1 a fter 1st vcc1 ov sbc restart mode 4 no ext. pull-up 0 1 1 x vcc1 ov 1 after 1st vcc1 ov sbc fail-safe mode
TLE9260QXV33 system features data sheet 24 rev. 1.1, 2014-10-23 5.1.1.2 sbc init mode in sbc init mode, the device waits fo r the microcontroller to finish its star tup and initializatio n sequence. in the sbc init mode any valid spi command will bring the sbc to sbc normal mode . during the long open window the watchdog has to be trigger ed. thereby the watchdog will be automatically configured. a missing watchdog trigger during th e long open window will cause a watchdog failure and the device will enter sbc restart mode. wake events are i gnored during sbc init mode and will therefore be lost. note: any spi command will bring the sbc to sbc norm al mode even if it is a illegal spi command (see chapter 14.2 ). note: for a safe start-up, it is recommended to use the fi rst spi command to trigger and to configure the watchdog (see chapter 13.2 ). note: at power up no vcc1_uv will be issued nor will fox be triggered as long as vcc1 is below the v rt,x threshold and if vs is below the vcc1 short circuit detection threshold v s,uv . the ro pin will be kept low as long as vcc1 is below the selected v rt,x threshold.
TLE9260QXV33 system features data sheet 25 rev. 1.1, 2014-10-23 5.1.2 sbc normal mode the sbc normal mode is the standard operating mode fo r the sbc. all configurations have to be done in sbc normal mode before entering a low-power mode (see also chapter 5.1.6 for the device configuration defining the fail-safe mode behavior). a wake-up event on can and wkx will create an interrupt on pin int - however, no change of the sbc mode will occur. the configuration options are listed below: ? vcc1 is active ? vcc2 can be switched on or off (default = off) ? can is configurable (off coming from sbc init mode ; off or wake capable coming from sbc restart mode, see also chapter 5.1.5 ) ? hs outputs can be switched on or off (default = off) or can be controlled by pwm; hs outputs are off coming from sbc restart mode ? wake pins show the input level and can be selected to be wake capable (interrupt) ? cyclic sense can be configured wit h hs1...4 and timer1 or timer 2 ? cyclic wake can be configured with timer1 or timer2 ? watchdog is configurable ? all fox outputs are off by default. coming from sbc rest art mode fox can be active (due to a failure event, e.g. watchdog trigger failure, vcc1 short circ uit, etc.) or inactive (no failure occurred) in sbc normal mode, there is the possibilit y of testing the fo outputs, i.e. to verify if setting the fo pin to low will create the intended behavior within the system. the fo ou tput can be enabled and then disabled again by the microcontroller by setting the fo_on spi bit. this feature is only intended for testing purposes.
TLE9260QXV33 system features data sheet 26 rev. 1.1, 2014-10-23 5.1.3 sbc stop mode the sbc stop mode is the first level technique to reduc e the overall current consumption by setting the voltage regulators vcc1, vcc2 into a low-power mode. in this mode vcc1 is still active and supplying the microcontroller, which can enter a power down mode. th e vcc2 supply, can mode as well as the hsx outputs can be configured to stay enabled. all kind of settings have to be done before entering sbc stop mode. in sbc stop mode any kind of spi write commands are ignored and the spi_fail bit is set, except for changing to sbc normal mode, triggering a sbc soft reset, refreshing the watchdog as well as for reading and clearing the spi status registers. a wake-up event on can and wkx will create an interr upt on pin int - however, no change of the sbc mode will occur. the conf iguration options are listed below: ? vcc1 is on ? vcc2 is fixed as configured in sbc normal mode ? can mode is fixed as configured in sbc normal mode ? wk pins are fixed as configured in sbc normal mode ? hs outputs are fixed as configured in sbc normal mode ? cyclic sense is fixed as c onfigured in sbc normal mode ? cyclic wake is fixed as co nfigured in sbc normal mode ? watchdog is fixed as configured in sbc normal mode ? sbc soft reset can be triggered ? fox outputs are fixed, i.e. the stat e from sbc normal mode is maintained an interrupt is triggered on the pin int when sbc stop mo de is entered and not all wake source signalization flags from wk_stat_1 and wk_stat_2 were cleared. note: if switches are enabled during sbc stop mode, e.g. hsx on with or without pwm, then the sbc current consumption will increase (see chapter 4.4 ). note: it is not possible to switch di rectly from sbc stop m ode to sbc sleep mode. do ing so will also set the spi_fail flag and will bring the sbc into restart mode. note: when wk1 and wk2 are configured fo r the alternate measurement function ( wk_meas = 1) then the wake inputs cannot be selected as wake input sources.
TLE9260QXV33 system features data sheet 27 rev. 1.1, 2014-10-23 5.1.4 sbc sleep mode the sbc sleep mode is the second level technique to reduce the overall current consumption to a minimum needed to react on wake-up events or for the sbc to perfor m autonomous actions (e.g. cyclic sense). in this mode, vcc1 is off and not supplying the microcontroller anymor e.the vcc2 supply as well as the hsx outputs can be configured to stay enabled. the setti ngs have to be done before entering sbc sleep mode. a wake-up event on can or wkx will bring the device via sbc restart mode into sbc normal mode again and signal the wake source. the configuration options are listed below: ? vcc1 is off ? vcc2 is fixed as configured in sbc normal mode ? can mode changes automatically from on or receive on ly mode to wake capable mode or can be selected to be off ? wk pins are fixed as configured in sbc normal mode ? hs outputs are fixed as configured in sbc normal mode ? cyclic sense is fixed as c onfigured in sbc normal mode ? cyclic wake is not available ? watchdog is off ? fox outputs are fixed, i.e. the stat e from sbc normal mode is maintained ? as vcc1 is off during sbc sleep mode, no spi communication is possible; ? the sleep mode entry is signalled in the spi register dev_stat with the bit dev_stat it is not possible to switch all wake source s off in sbc sleep mode. doing so will set the spi_fail flag and will bring the sbc into sbc restart mode. in order to enter sbc sleep mode successfully , all wake source signalization flags from wk_stat_1 and wk_stat_2 need to be cleared. a failure to do so will result in an immediate wake-u p from sbc sleep mode by going via sbc restart to normal mode. all settings must be done before entering sbc sleep mode. note: if switches are enabled during sbc sleep mode, e.g. hsx on with or without pwm, then the sbc current consumption will increase (see chapter 4.4 ). note: cyclic sense function will not work properly anymore in case of an over current, over temper ature, under- or overvoltage (in case function is se lected) event because the respecti ve hs switch will be disabled. note: when wk1 and wk2 are configured fo r the alternate measurement function ( wk_meas = 1) then the wake inputs cannot be selected as wake input sources.
TLE9260QXV33 system features data sheet 28 rev. 1.1, 2014-10-23 5.1.5 sbc restart mode there are multiple reasons to enter the sbc restart mode . the purpose of the sbc rest art mode is to reset the microcontroller: ? in case of under voltage on vcc1 in sbc normal and in sbc stop mode, ? in case of over voltage on vcc1 if the bit vcc1_ov_rst is set and if cfgp = ?1?, ? due to 1st incorrect watchdog triggering (only if confi g1, config3 or config 4 is selected, otherwise sbc fail- safe mode is immediately entered), ? in case of a wake event from sbc sleep or sbc fail-safe mode or a release of over temperature shutdown (tsd2) out of sbc fail-safe mode this transition is used to ramp up vcc1 after a wake in a defined way. from sbc restart mode, the sbc goes au tomatically to sbc normal mode, i.e the mode is left automatically by the sbc without any microcon troller influence. the sbc mode bits are cleared. as shown in figure 35 the reset output (ro) is pulled low when entering restart mode and is released at the transiti on to normal mode after the reset delay time ( t rd1 ). the watchdog timer will start with a long open wi ndow starting from th e moment of the rising edge of ro and the watchdog per iod setting in the register wd_ctrl will be changed to the respective default value ?100?. leaving the sbc restart mode will not result in ch anging / deactivating the fail outputs. the behavior of the blocks is listed below: ? all fox outputs are activated in case of a 1st watchdog trigger failure (if config1 or config2 is selected) or in case of vcc1 over voltage detection (if vcc1_ov_rst is set) ? vcc1 is on or ramping up ? vcc2 will be disabled if it was activated before ? can is ?woken? due to a wake event or off depending on previous sbc and transceiver mode (see also chapter 9 ). it is wake capable when it was in can normal-, receive only or wake capable mode before sbc restart mode ? hs outputs will be disabled if they were activated before ? ro is pulled low during sbc restart mode ? spi communication is ignored by th e sbc, i.e. it is not interpreted ? the restart mode entry is signalled in the spi register dev_stat with the bits dev_stat note: an over voltage event on vcc1 will only lead to sbc rest art mode if the bit vcc1 _ov_rst is set and if cfgp = ?1? (config 1/3). note: the content of the wd_fail bits will depend on the devic e configuration, e.g. 1 or 2 watchdog failures. table 7 reasons for restart - state of spi status bits after return to normal mode prev. sbc mode event dev_stat wd_fail vcc1_uv vcc1_ov vcc1_sc normal 1x watchdog failure 01 01 x x x normal 2x watchdog failure 01 10 x x x normal vcc1 under voltage reset 01 xx 1 x x normal vcc1 over voltage reset 01 xx x 1 x stop 1x watchdog failure 01 01 x x x stop 2x watchdog failure 01 10 x x x stop vcc1 under voltage reset 01 xx 1 x x stop vcc1 over voltage reset 01 xx x 1 x sleep wake-up event 10 xx x x x fail-safe wake-up event 01 see ?reasons for fail safe, table 8 ?
TLE9260QXV33 system features data sheet 29 rev. 1.1, 2014-10-23 5.1.6 sbc fail-safe mode the purpose of this mode is to bring the system in a safe status after a failure condition by turning off the vcc1 supply and powering off the microcontroller. after a wa ke event the system is then able to restart again. the fail-safe mode is automatically reached for following events: ? after an sbc thermal shutdown (tsd2) (see also chapter 13.9.3 ), ? in case of over voltage on vcc1 if the bit vcc1_ov_rst is set and if cfgp = ?0?, ? after a 1st incorrect watchdog trigger in config2 ( cfg = 1) and after a 2nd incorrect watchdog trigger in config4 ( cfg = 0) (see also chapter 5.1.1 ), ? if vcc1 is shorted to gnd (see also chapter 13.7 ), ? after 4 consecutive vcc1 unde r voltage events (only if vs > v s,uv , see chapter 13.6 ). in this case, the default wake sources (can, wk1. ..3, see also registers wk_ctrl_2 , bus_ctrl_1 ) are activated, the wake events are cleared in the register wk_stat_1 , and all output drivers and all voltage regulators are switched off. when wk1 and wk2 are configured for the alternate measurement function ( wk_meas = 1) then wk1 and wk2 will stay configured for the measurement fu nction when sbc fail-safe mode is entered, i.e. they will not be activated as wake sources. the sbc fail-safe mode will be maintained until a wake event on the default wake sources occurs. to avoid any fast toggling behavior a filter time of typ. 100ms ( t fs,min ) is implemented. wake ev ents during this time will be stored and will automatically l ead to entering sbc restart mode after the filter time. in case of an vcc1 over temperatur e shutdown (tsd2) the sbc restart mo de will be reached au tomatically after a filter time of typ. 1s ( t tsd2 ) without the need of a wake event. leaving the sbc fail-safe mode will not result in deactivati on of the fail output pins. the following functions are influenced during sbc fail-safe mode: ? all fox outputs are activated (see also chapter 12 ) ? vcc1 is off ? vcc2 is off ? can is wake capable ? hs outputs are off ? wk pins are wake capable through static sense (with default 16s filter time) ? cyclic sense and cyclic wake is disabled ? spi communication is disabled because vcc1 is off ? the fail-safe mode activation is signalled in the spi register dev_stat with the bits failure and dev_stat
TLE9260QXV33 system features data sheet 30 rev. 1.1, 2014-10-23 note: an over voltage event on vcc1 will only lead to sbc fail-safe mode if the bit vcc1_ov_rst is set and if cfgp = ?0? (config 2/4). note: the content of the wd_fail bits will depend on the devic e configuration, e.g. 1 or 2 watchdog failures. note: see chapter 13.6.1 for detailed description of the 4x vcc1 under voltage behavior. 5.1.7 sbc development mode the sbc development mode is used during the developme nt phase of the module. it is especially useful for software development. compared to the default sbc user mode operation, this mode is a super set of the state machin e. the device will start also in sbc init mode and it is possible to use all the sbc modes and functions with following differences: ? watchdog is stopped and does not need to be triggered. therefore no reset is triggered due to watchdog failure ? sbc fail-safe and sbc restart mode are not reached du e to watchdog failure but the other reasons to enter these modes are still valid ? can and vcc2 default value in sbc init mode and entering sbc normal mode fr om sbc init mode is on instead of off the sbc software development mode is reached automati cally if the fo3/test pin is set and kept low during sbc init mode. the voltage level moni toring is started as soon as vs > v por,f . the software development mode is configured and maintained if sbc init mode is left by sending any spi command while fo3/test is low. in case the fo3/test level will be high for longer than t test during the monitoring period then the sbc development mode is not reached . the sbc will remain in this mode for all conditions and can only be le ft by powering down the device (vs < v por,f ). table 8 reasons for fail-safe - state of spi status bits after return to normal mode prev. sbc mode failure event dev_ stat tsd2 wd_ fail vcc1_ uv vcc1_ uv_fs vcc1_ ov vcc1_ sc normal 1 x watchdog failure 01 x 01 x x x x normal 2 x watchdog failure 01 x 10 x x x x normal tsd2 01 1 xx x x x x normal vcc1 short to gnd 01 x xx 1 x x 1 normal 4x vcc1 uv 01 x xx 1 1 x x normal vcc1 over voltage 01 x xx x x 1 x stop 1 x watchdog failure 01 x 01 x x x x stop 2 x watchdog failure 01 x 10 x x x x stop tsd2 01 1 xx x x x x stop vcc1 short to gnd 01 x xx 1 x x 1 stop 4x vcc1 uv 01 x xx 1 1 x x stop vcc1 over voltage 01 x xx x x 1 x
TLE9260QXV33 system features data sheet 31 rev. 1.1, 2014-10-23 5.2 wake features following wake sources are implemented in the device: ? static sense: wk inputs are permanently active (see chapter 10 ) ? cyclic sense: wk inputs only active duri ng on-time of cyclic sense period (see below) ? cyclic wake: internal wake source co ntrolled via internal timer (see below) ? can wake: wake-up via can message (see chapter 9 ) 5.2.1 cyclic sense the cyclic sense feature is intended to reduce the qu iescent current of the device and the application. in the cyclic sense configuration, one or more high-s ide drivers are switched on periodically controlled by timer1_ctrl and timer2_ctrl . the respective high-side drivers supp ly external circuitries e.g. switches and/or resistor arrays, which are connect ed to one or more wake inputs (see figure 5 ). any edge change of the wkx input signal during the on-time of the cyclic sense period causes a wake. depending on the sbc mode, either the int is pulled low (sbc normal mode and stop mode) or the sbc is woken enabling the vcc1 (after sbc sleep and sbc fail-safe mode). figure 5 cyclic sense working principle switching circuitry 1-4 high side hs x wk x sbc state machine gnd wk 1-3 wk_flt_ctrl hs_ctrl timer_ctrl period / on-time signals to uc int
TLE9260QXV33 system features data sheet 32 rev. 1.1, 2014-10-23 5.2.1.1 configuration and op eration of cyclic sense the correct sequence to configure the cyclic sense is shown in figure 6 . all the configurations have to be performed before the on-time is set in the timerx_ctrl registers. the sett ings ?off / low? and ?off / high? define the voltage level of the respective hs driver be fore the start of the cyclic sense. the intention of this selection is to avoid an unintentional wake due to a voltage level change at the start of the cyclic sense. cyclic sense (=timerx) will start as so on as the respective on- time has been selected independently from the assignment of the hs and filter co nfiguration. the selection of the respective timer (config c/d see chapter 10.2.1 ) must therefore be done before starting the ti mer. the correct configuration sequence is as follows: ? configure the initial level ? mapping of a timer to the respective hsx outputs ? configuring the respective filter timing and wk pins ? configuring the timer period and on-time figure 6 cyclic sense: configuration and sequence note: all configurations of period and on-time can be se lected. however, recommended on-times for cyclic sense are 0.1ms, 0.3ms and 1ms. the sp i_fail will be set if the on-tim e is longer than the period. cyclic sense configuration assign timer to selected hs switch in hs_ctrl_x enable wkx as wake source with configured timer in wk_flt_ctrl cyclic sense starts / ends by setting / clearing on-time timer1, timer2 select timer period and desired on-time in timerx_ctrl wk1, wk2, wk3 with above selected timer period : 10, 20, 50, 100, 200ms, 1s, 2s on-time: 0.1, 0.3, 1.0, 10, 20ms assign timerx_on to off/low or off/high in timerx_ctrl timer1, timer2 select wkx pull-up / pull-down configuration in wk_pupd_ctrl no pull -up/-down, pull -down or pull -up selected, automatic switching changing the settings can be done on the fly, changes become effective at the next on-time or period
TLE9260QXV33 system features data sheet 33 rev. 1.1, 2014-10-23 the first sample of the wk input value (high or low) is taken as the reference for the next cycle. a change of the wk input value between the first and second cycle recognized duri ng the on-time of the second cycle will cause a wake from sbc sleep mode or an interrupt during sbc normal or sbc stop mode. a filter time of 16s is implemented to avoid a parasitic wake-up due to tran sients or emc disturbances. the filter time t fwk1 is triggered right at the end of the selected on-time and a wake signal is recognized if: ? the input level will not cross the switchi ng threshold level of typ. 3v during th e selected filter time (i.e. if the signal will keep the high or low level) and ? there was an input level change betw een the current and previous cycle
TLE9260QXV33 system features data sheet 34 rev. 1.1, 2014-10-23 a wake event due to cyclic sense in sbc mode will se t the respective bit wk1_ wu, wk2_wu, or wk3_wu. during cyclic sense, wk_lvl_stat is updated only with the sampled voltage levels of the wkx pins in sbc normal or sbc stop mode. the functionality of the sampling and different scenarios are depicted in figure 7 to figure 9 . the behavior in sbc stop and sbc sleep mode is identical except that in stop mode int will be triggered to signal a change of wk input levels and in sbc sleep mode, vcc1 will po wer-up instead. figure 7 wake input timing figure 8 cyclic sense example in sbc stop m ode, hsx starts ?off?/low, gnd based wkx input filter time t fwk1 on time periode hs switch t filter time t fwk1 hs on cyclic sense 1st sample taken as reference wake detection possible on 2nd sam ple high n-1 low open closed filter time int & wk bit set learning cycle wk n-1 = high wk n = low wk n wk n-1 wake event wk n+1 = low wk n = wk n+1 no wake wk n+2 = high wk n+2 wk n+ 1 wake event nn+1n+2 hs wk high low switch int high low
TLE9260QXV33 system features data sheet 35 rev. 1.1, 2014-10-23 figure 9 cyclic sense example in sbc sleep mode, hsx starts ?off?/high, gnd based wkx input the cyclic sense function will no t work properly anymore in case of followin g conditions: ? in case sbc fail-safe mode is entered: the res pective hs switch will be disabl ed and the respective wake pin will be changed to static sensing ? in sbc normal, stop, or sleep mode in case of an ov ercurrent, overtemperature, under- or overvoltage (in case function is selected ) event: the respective hs switch will be disabled note: the internal timers for cyclic sense are not disabled automatically in case the hs switch is turned off due to above mentioned failures.this must be considered to avoid loss of wake events. 5.2.1.2 cyclic sense in low power mode if cyclic sense is intended for sbc stop or sbc sleep mo de mode, it is necessary to activate the cyclic sense in sbc normal mode before going to the low power mo de. a wake event due to cyclic sense will set the respective bit wk1_wu, wk2_wu or wk3_wu. in stop mode the wake event will trigge r an interrupt, in sleep mode the wake event will send the device via re start mode to normal mode. before re turning to sbc sleep mode, the wake status register wk_stat_1 and wk_stat_2 needs to be cleared. trying to go to sbc sleep mode with uncleared wake flags, such as wkx_wu the sbc will di rectly wake-up from sleep mode by going via restart mode to normal mode, a reset is issued. the wkx_wu bi t is seen as source for the wake. this is implemented in order not to loose an wake event during the transition. start of cyclic sense high n-1 low open closed filter tim e int & wk bit set learning cycle wk n-1 = low wk n = low wk n = wk n-1 no wake event wk n = wk n+1 = low ( but ignor ed because change during filter time ) wk n = wk n+1 no wake event wk n+2 = high wk n+2 wk n+ 1 wake event nn+1 n+2 hs wk high low switch high low vcc1 sbc sleep mode sp ike transition to: sbc normal mode
TLE9260QXV33 system features data sheet 36 rev. 1.1, 2014-10-23 5.2.2 cyclic wake the cyclic wake feature is intended to reduce th e quiescent current of the device and application. for the cyclic wake feature one or bo th timers are configured as internal wake-up so urce and will periodically trigger an interrup t in sbc normal and sbc stop mode. the correct sequence to configure the cyclic wake is shown in figure 10 . the sequence is as follows: ? first, disable the timers to ensure that there is no t unintentional interrupt wh en activating cyclic wake, ? enable timer1 and/or timer2 as a wake-up source in the register wk_ctrl_1 , ? configure the respective period timer1 and/or timer2. al so an on-time (any value) mu st be selected to start the cyclic wake even if the value is ignored. figure 10 cyclic wake: configuration and sequence as in cyclic sense, the cyclic wake function will start as soon as the on-time is configured. an in terrupt is generated for every start of the on time except for th e very first time when the timer is started cyclic wake configuration cyclic wake starts / ends by setting / clearing on-time int is pulled low at every rising edge of on-time except first one select timer period and any on-time in timerx_ctrl periods : 10, 20, 50, 100, 200 ms, 1s, 2s on-times: any (off/low & off/high are not allowed ) disable timer1 and/or timer2 as a wake source in wk_ctrl_1 to avoid unintentional interrupts select timer1 and/or timer2 as a wake source in wk_ctrl_1 no interrupt will be generated , if the timer is not enabled as a wake source
TLE9260QXV33 system features data sheet 37 rev. 1.1, 2014-10-23 5.2.3 internal timer the integrated timer1 and timer2 are typically used to wake up the microcontroller periodically (cyclic wake) or to perform cyclic sense on the wake inputs. therefore, the ti mers can be mapped to the dedicated hs switches by spi (via hs_ctrl1 ...2). following periods and on-times can be selected via the register timer1_ctrl and timer2_ctrl respectively: ? period: 10ms / 20ms / 50ms / 100ms / 200ms / 1s / 2s ? on time: 0.1ms / 0.3ms / 1.0ms / 10m s / 20ms / off at high or low 5.3 supervision features the device offers various supervision features to support functional safety requirements. please see chapter 13 for more information.
data sheet 38 rev. 1.1, 2014-10-23 TLE9260QXV33 voltage regulator 1 6 voltage regulator 1 6.1 block description figure 11 module block diagram functional features ? 3.3v low-drop voltage regulator ? under voltage monitoring with adjust able reset level, vcc1 prewarning and vcc1 short circuit detection ( v rt1/2/3/4 , v pw,f ). please refer to chapter 13.6 and chapter 13.7 for more information. ? short circuit detection and switch off with under volt age fail threshold, device enters sbc fail-safe mode ? 470nf ceramic capacitor at voltage outp ut for stability, with esr < 1 ? @ f = 10 khz, to achieve the voltage regulator control lo op stability based on the safe phase margin (bode diagram). ? output current capability up to i vcc1,lim . gnd overt emperat ure shutdown 1 bandgap reference vs state machine vcc1 inh vref
data sheet 39 rev. 1.1, 2014-10-23 TLE9260QXV33 voltage regulator 1 6.2 functional description the voltage regulator 1 (=vcc1) is ?o n? in sbc normal and sbc stop mode and is disabled in sbc sleep and in sbc fail-safe mode. the regulator can provide an output current up to i vcc1,lim . for low-quiescent current reasons, the output voltage to lerance is decreased in sbc stop mode because only a low-power mode regulator with a lower accuracy ( v cc1,out41 ) will be active for small lo ads. if the load current on vcc1 exceeds the selected threshold ( i vcc1,ipeak1,r or i vcc1,ipeak2,r ) then the high-power m ode regulator will be also activated to suppor t an optimum dynamic load behavio r. the current consumption will th en increase by typ. 2.9ma. if the load current on vcc1 falls below the selected threshold ( i vcc1,ipeak1,f or i vcc1,ipeak2,f ), then the low-quiescent current mode is resumed again by disabling the high-power mode regulator. both regulators (low-power mode and high-power mode) are active in sbc normal mode. two different active peak thre sholds can be selected via spi: ? i_peak_th = ?0?(default): the lower vcc1 ac tive peak threshold 1 is selected with lowest quiescent current consumption in sbc stop mode ( i stop_1,25 , i stop_1,85 ); ? i_peak_th = ?1?: the higher vcc1 active peak threshold 2 is selected with an increased quiescent current consumption in sbc stop mode ( i stop_2,25 , i stop_2,85 );
data sheet 40 rev. 1.1, 2014-10-23 TLE9260QXV33 voltage regulator 1 6.3 electrical characteristics table 9 electrical characteristics v s = 5.5 v to 28 v; t j = -40 c to +150 c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. output voltage including line and load regulation (vcc1 = 3.3v) v cc1,out5 3.23 3.3 3.37 v 1) sbc normal mode; 10a < i vcc1 < 250ma 6v < v s < 28v 1) in sbc stop mode, the specified out put voltage tolerance applies when i vcc1 has exceeded the selected active peak threshold (i vcc1,ipeak1,r or i vcc1,ipeak2,r ) but with increased current consumption. p_6.3.14 output voltage including line and load regulation v cc1,out8 3.23 3.3 3.37 v 1) sbc normal mode; 10a < i vcc1 < 150ma p_6.3.22 output voltage including line and load regulation (vcc1 = 3.3v) v cc1,out6 3.29 ? 3.35 v 1)2) sbc normal mode; 20ma < i vcc1 < 80ma 8v < v s < 18v 25c < t j < 125c p_6.3.15 output voltage including line and load regulation (vcc1 = 3.3v) v cc1,out71 3.29 3.3 3.43 v sbc stop mode; 1ma < i vcc1 < i vcc1,ipeak p_6.3.16 output voltage including line and load regulation (vcc1 = 3.3v) v cc1,out72 3.29 3.3 3.47 v sbc stop mode; 10a < i vcc1 < 1ma p_6.3.21 output drop v cc1,d1 ?? 500mv i vcc1 = 50ma v s =3v p_6.3.3 output drop v cc1,d2 ?? 500mv i vcc1 = 150ma v s =5v p_6.3.4 vcc1 active peak threshold 1 (transition threshold between low-power and high-power mode regulator) i vcc1,ipeak1,r ?1.93.5ma 2) i cc1 rising; v s = 13.5v -40c < t j < 150c; i_peak_th = ?0? p_6.3.13 vcc1 active peak threshold 1 (transition threshold between high-power and low-power mode regulator) i vcc1,ipeak1,f 0.5 1.3 ? ma 2) i cc1 falling; v s = 13.5v -40c < t j < 150c; i_peak_th = ?0? p_6.3.17 vcc1 active peak threshold 2 (transition threshold between low-power and high-power mode regulator) i vcc1,ipeak2,r ?4.37.0ma 2) i cc1 rising; v s = 13.5v -40c < t j < 150c; i_peak_th = ?1? p_6.3.18 vcc1 active peak threshold 2 (transition threshold between high-power and low-power mode regulator) i vcc1,ipeak2,f 1.7 3.4 ? ma 2) i cc1 falling; v s = 13.5v -40c < t j < 150c; i_peak_th = ?1? p_6.3.19 over current limitation i vcc1,lim 250 ? 1200 2) ma current flowing out of pin, v cc1 = 0v p_6.3.6
data sheet 41 rev. 1.1, 2014-10-23 TLE9260QXV33 voltage regulator 1 figure 12 typical on-resistance characterization resu lts of vcc1 pass device during low drop operation for i cc1 = 100ma 2) not subject to production test, specified by design.
data sheet 42 rev. 1.1, 2014-10-23 TLE9260QXV33 voltage regulator 1 figure 13 characterization results of on-resistance range of vcc1 pass device during low drop operation for i cc1 = 150ma
data sheet 43 rev. 1.1, 2014-10-23 TLE9260QXV33 voltage regulator 2 7 voltage regulator 2 7.1 block description figure 14 module block diagram functional features ? 5 v low-drop voltage regulator ? protected against short to battery voltage, e.g. for off-board sensor supply ? can also be used for can supply ? vcc2 under voltage monitoring. please refer to chapter 13.8 for more information ? can be active in sbc normal, sbc stop, and sbc sleep mode (not sbc fail-safe mode) ? vcc2 switch off after entering sbc restart mode. switch off is latched, ldo must be enabled via spi after shutdown. ? over temperature protection ? 470nf ceramic capacito r at output voltage fo r stability, with esr < 1 ? @ f = 10 khz, to achieve the voltage regulator control lo op stability based on the safe phase margin (bode diagram). ? output current capability up to i vcc2,lim . gnd overtemperature shutdown 1 bandgap reference vs state machine vcc2 inh vref
data sheet 44 rev. 1.1, 2014-10-23 TLE9260QXV33 voltage regulator 2 7.2 functional description in sbc normal mode vcc2 can be switched on or off via spi. for sbc stop- or sleep mode, the vcc2 has to be switch ed on or off before entering the respective sbc mode. the regulator can provide an output current up to i vcc2,lim . for low-quiescent current reasons, the output voltage to lerance is decreased in sbc stop mode because only a low-power mode regulator with a lower accuracy ( v cc2,out5 ) will be active for small load s. if the load current on vcc2 exceeds i vcc2 > i vcc2,ipeak,r then the high-power mode regulator will al so be enabled to support an optimum dynamic load behavior. the current consumption will then increase by typ. 2.9ma. if the load current on vcc2 falls below the threshold ( i vcc2 < i vcc2,ipeak,f ), then the low-quiescent current mode is resumed again by disabling the high-power mode regulator. both regulators are active in sbc normal mode. note: if the vcc2 output voltage is supplying external off-board loads, the application must consider the series resonance circuit built by cable inductance and decoup ling capacitor at the load. sufficient damping must be provided. 7.2.1 short to battery protection the output st age is protected for short to vbat.
data sheet 45 rev. 1.1, 2014-10-23 TLE9260QXV33 voltage regulator 2 7.3 electrical characteristics table 10 electrical characteristics v s = 5.5 v to 28 v; t j = -40 c to +150 c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. output voltage including line and load regulation (sbc normal mode) v cc2,out1 4.9 5.0 5.1 v 1) sbc normal mode; 10a < i vcc2 < 100ma 6.5v < v s < 28v 1) in sbc stop mode, the specified out put voltage tolerance applies when i vcc2 has exceeded the selected active peak threshold (i vcc2,ipeak,r ) but with increased current consumption. p_7.3.1 output voltage including line and load regulation (sbc normal mode) v cc2,out2 4.9 5.0 5.1 v 1) sbc normal mode; 10a < ivcc2 < 80ma 6v < vs < 28v p_7.3.16 output voltage including line and load regulation (sbc normal mode) v cc2,out3 4.9 5.0 5.1 v 1) sbc normal mode; 10a < i vcc2 < 40ma p_7.3.2 output voltage including line and load regulation (sbc normal mode) v cc2,out4 4.97 ? 5.07 v 2) sbc normal mode; 10a < i vcc2 < 5ma 8v < v s < 18v 25c < t j < 125c 2) not subject to production test, specified by design. p_7.3.14 output voltage including line and load regulation (sbc stop/sleep mode) v cc2,out5 4.9 5.05 5.2 v stop, sleep mode; 1ma < i vcc2 < i vcc2,ipeak p_7.3.3 output voltage including line and load regulation (sbc stop/sleep mode) v cc2,out6 4.9 5.05 5.25 v stop, sleep mode; 10a < i vcc2 < 1ma p_7.3.18 output drop v cc2,d1 ??500mv i vcc2 = 30ma v s = 5v p_7.3.4 vcc2 active peak threshold (transition threshold between low-power and high-power mode regulator) i vcc2,ipeak,r ?1.93.5ma 2) i cc2 rising; v s = 13.5v -40c < t j < 150c p_7.3.15 vcc2 active peak threshold (transition threshold between high-power and low-power mode regulator) i vcc2,ipeak,f 0.5 1.3 ? ma 2) i cc2 falling; v s = 13.5v -40c < t j < 150c p_7.3.17 over current limitation i vcc2,lim 100 ? 750 2) ma current flowing out of pin, v cc2 = 0v p_7.3.5
data sheet 46 rev. 1.1, 2014-10-23 TLE9260QXV33 voltage regulator 2 figure 15 typical on-resistance of vcc2 pa ss device during low drop operation for i cc2 = 30ma
data sheet 47 rev. 1.1, 2014-10-23 TLE9260QXV33 voltage regulator 2 figure 16 on-resistance range of vcc2 pass device during low drop operation for i cc2 = 50ma
data sheet 48 rev. 1.1, 2014-10-23 TLE9260QXV33 high-side switch 8 high-side switch 8.1 block description figure 17 high-side module block diagram features ? dedicated supply pin vshs for high-side outputs ? over voltage and under voltage switch off - configurable via spi ? overcurrent detection and switch off ? open load detection in on-state ? pwm capability with internal timer configurable via spi ? switch recovery after removal of ov or uv condition configurable via spi 8.2 functional description the high-side switches can be used for control of leds, as supply for the wake inputs and for other loads. the high-side outputs can be controlle d either directly via spi by ( hs_ctrl1 , hs_ctrl2 ), by the integrated timers or by the integrated pwm generators. the high-side outputs are supplied by a dedicated supply pin vshs (different to vs). the topology supports improved cranking condition behavior. the configuration of the high-side (permanent on, pwm, cyclic sense, etc.) drivers mu st be done in sbc normal mode. the configuration is taken over in sbc stop- or sbc sleep mode and cannot be modified. when entering sbc restart mode or sbc fail-safe mode the hsx outputs are disabled. hs gate control overcurrent det ect ion open load (on) vshs hsx
data sheet 49 rev. 1.1, 2014-10-23 TLE9260QXV33 high-side switch 8.2.1 over and under voltage switch off all hs drivers in on-state are switched off in case of over voltage on vshs ( v shs,ovd ). if the voltage drops below the over voltage threshold the hs drivers are activated ag ain. the feature can be disabled by setting the spi bit hs_ov_sd_en . the hs drivers are switched off in case of under voltage on vshs ( v shs,uvd ). if the voltage rises above the under voltage threshold the hs drivers are activated again. the feature can be disabled by setting the spi bit hs_uv_sd_en . so after release of under voltage or over voltage conditio n the hs switch goes back to programmed state in which it was configured via spi. this b ehavior is only valid if the bit hs_ov_uv_rec is set to ?1?. otherwise the switches will stay off and the respective spi control bits are cleared are cleared. the over voltage and under volt age is signaled in the bits vshs_ov and vshs_uv , no other error bits are set. 8.2.2 over current det ection and switch off if the load current exceeds the over current shutdown th reshold for a time longer then the over current shutdown filter time the output is switched off. the over current condition and the switch off is signaled with the respective hsx_oc_ot bit in the register hs_oc_ot_stat . the hsx configuration is then reset to 000 by the sbc. to activate the high-side again the hsx configuration has to be set to on (001) or be progr ammed to a timer function. it is recommended to clear the over current bit before activation the high-side switch, as the bits are not cleared automatically by the sbc. 8.2.3 open load detection open load detection on the high-side outputs is done during on state of the output. if the current in the activated output falls below then open load detection current, the open load is detected and signaled via the respective bit hs1_ol, hs2_ol, hs3_ol, or hs4_ol in the register hs_ol_stat . the high-side output stays activated. if the open load condition disappears the open load bit in the spi can be cleared. the bits are not cleared automatically by the sbc. 8.2.4 hsx operation in different sbc modes ? during sbc stop and sbc sleep mode the hsx outputs ca n be used for the cyclic sense feature. the open- load detection, over current shut down as well as over voltage and under voltage shutdown are available. the over current shutdown pr otection feature may infl uence the wake-up behavior 1) . ? the hsx output can also be enabled for sbc stop and sbc sleep mode as well as controlled by the pwmx generator. the hsx outputs must be configured in sbc normal mode before entering a low-power mode. ? the hsx outputs are switched off during sbc restart or sbc fail-safe mode. they can be enabled via spi if the failure condit ion is removed. 1) for the wake feature, the forced over current shut down case must be considered in the user software for all sbc modes, i.e. due to disabled hsx switches a level change might not be detected anymore at wkx pins.
data sheet 50 rev. 1.1, 2014-10-23 TLE9260QXV33 high-side switch 8.2.5 pwm and timer function two 8-bit pwm generators are dedicated to generate a pwm signal on the hs outp uts, e.g. for brightness adjustment or compensation of supply voltage fluctuat ion. the pwm generators are mapped to the dedicated hs outputs, and the duty cycle can be independently configured with a 8bit resolution via spi ( pwm1_ctrl , pwm2_ctrl ). two different frequencies (200hz, 400hz) can be selected independently for every pwm generator in the register pwm_freq_ctrl . pwm assignment and configuration: ? configure duty cycle and frequency for respecti ve pwm generator in pwm1_ctrl / pwm2_ctrl and pwm_freq_ctrl ? assign pwm generator to respecti ve hs switch(es) in hsx_ctrl ? the pwm generation will start right after the hsx is assigned to the pwm generator ( hs_ctrl1 , hs_ctrl2 ) assignment options of hs1... hs4 ?timer 1 ?timer 2 ?pwm 1 ?pwm 2 note: the min. on-time during pwm is limited by the actual ton and toff time of the respective hs switch, e.g. the pwm setting ?0000 0001? could not be realized. in addition, the minimum pwm setting for reliable detecti on of over-current and open-load measurement is 4 digits for a period of 400hz and 2 digits for a period of 200hz
data sheet 51 rev. 1.1, 2014-10-23 TLE9260QXV33 high-side switch 8.3 electrical characteristics table 11 target specifications v s = 5.5 v to 28 v; t j = -40 c to +150 c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. output hs1, hs2, hs3, hs4 static drain-source on resistance hs1...hs4 r on,hs25 ?7? ? i ds = 60ma, t j < 25c p_9.3.1 static drain-source on resistance hs1...hs4 r on,hs150 ? 11.5 16 ? i ds = 60ma, t j < 150 c p_9.3.2 leakage current hsx / per channel i leak,hs ??2a 1) 0 v < vhsx < vshs; tj < 85c p_9.3.11 output slew rate (rising) sr raise,hs 0.8 ? 2.5 v/s 1) 20 to 80% v shs = 6 to 18v r l = 220 ? 1) not subject to production test, specified by design. p_9.3.3 output slew rate (falling) sr fall,hs -2.5 ? -0.8 v/s 1) 80 to 20% v shs = 6 to 18v r l = 220 ? p_9.3.4 switch-on time hsx t on,hs 3 ? 30 s csn = high to 0.8*vshs; r l = 220 ? ; v shs = 6 to 18v p_9.3.5 switch-off time hsx t off,hs 3 ? 30 s csn = high to 0.2*vshs; r l = 220 ? ; v shs = 6 to 18v p_9.3.6 short circuit shutdown current i sd,hs 150 245 300 ma v shs = 6 to 20v, hysteresis included p_9.3.7 short circuit shutdown filter time t sd,hs 16 s 2) , 3) 2) not subject to production test, tolerance defined by internal oscillator tolerance. 3) the minimum pwm setting for reliable detection of over curr ent and open load measurement is 4 digits for a period of 400hz and 2 digits for a period of 200hz. p_9.3.8 open load detection current i ol,hs 0.4 ? 3 ma hysteresis included p_9.3.9 open load detection hysteresis i ol,hs,hys ?0.45?ma 1) p_9.3.14 open load detection filter time t ol,hs ?64?s 2) , 3) p_9.3.10
data sheet 52 rev. 1.1, 2014-10-23 TLE9260QXV33 high speed can transceiver 9 high speed can transceiver 9.1 block description figure 18 functional block diagram 9.2 functional description the controller area network (can) transceiver part of th e sbc provides high-speed (hs) differential mode data transmission (up to 2 mbaud) and reception in automotive and industrial applications. it works as an interface between the can protocol controller and the physical bu s lines compatible to iso/dis 11898-2, 11898-5 and sae j2284. the can transceiver offers low power modes to reduce cu rrent consumption. this supports networks with partially powered down nodes. to support software diagnostic fu nctions, a can receive-only mode is implemented. it is designed to provide excellent passive behavior when the transceiver is switched off (mixed networks, clamp15/30 applications). a wake-up from the can wake capable mode is possible via a message on the bus. thus, the microcontroller can be powered down or idled and will be woken up by the can bus activities. the can transceiver is designed to withstand the severe conditions of automotive applications and to support 12 v applications. the different transceiver modes can be controlled via the spi can bits. txdcan output stage driver temp.- protection canh canl + timeout rxdcan receiver mux v cc 1 spi mode control to spi diagnostic vc an v cc1 r txd wake receiver vs vcan v bias = 2.5v
data sheet 53 rev. 1.1, 2014-10-23 TLE9260QXV33 high speed can transceiver figure 19 shows the possible transceiver mode transitions when changing the sbc mode. figure 19 can mode control diagram can fd support can fd stands for ?can with flexible data rate?. it is based on the well established can protocol as specified in iso 11898-1. can fd still uses the can bus arbitration method. the benefit is that the bit rate can be increased by switching to a shorter bit time at the end of the arbitration process and then to return to the longer bit time at the crc delimiter, before the receivers tr ansmit their acknowledge bits. see also figure 20 . in addition, the effective data rate is increased by allowing longer data fiel ds. can fd allows the transmission of up to 64 data bytes compared to the 8 data bytes from the standard can. figure 20 bite rate increase with can fd vs. standard can not only the physical layer must support can fd but also the can controller. in case the can controller is not able to support can fd then the respective can node mu st at least tolerate can fd communication. this can fd tolerant mode is realized in th e physical layer in combination with ca n partial networking. the tle926x-3qx variants of this family also su pport the can fd tolerant mode. sbc normal mode sbc mode can tr ansceiver mode sbc stop mode sbc sleep mode sbc restart mode receive only normal mode off wake capable receive only off wake capable off woken 1 off wake capable 1 after a wake event on can bus normal mode behavior after sbc restart mode - not coming from sbc sleep mode due to a wake up of the respective transceiver : if the transceivers had been configured to normal mode, or receive only mode, then the mode will be changed to wake capable. if it was wake capable, then it will remain wake capable. if it had been off before sbc restart mode, then it will remain off. behavior in sbc development mode : can default value in sbc init mode and entering sbc normal mode from sbc init mode is on instead of off . sbc fail-safe mode wake capable example: - 11bit identifier + 8byte data - arbitration phase 500kbps - data phase 2mbps average bit rate 1.14mbps can header data phase (byte 0 ? byte 7) can footer standard can message can header data phase (byte 0 ? byte 7) can footer can fd with reduced bit time
data sheet 54 rev. 1.1, 2014-10-23 TLE9260QXV33 high speed can transceiver 9.2.1 can off mode the can off mode is the default mode after power-up of the sbc. it is available in all sbc modes and is intended to completely stop can activities or when can communication is not needed. the canh/l bus interface acts as a high impedance input with a very sm all leakage current. in can off mo de, a wake-up event on the bus will be ignored. 9.2.2 can normal mode the can transceiver is enabled via spi in sbc norma l mode. can normal mode is designed for normal data transmission/reception within the hs-can network. the mo de is available in sbc normal mode and in sbc stop mode. the bus biasing is set to vcan/2. transmission the signal from the microcontroller is applied to the txdcan input of the sbc. t he bus driver switches the canh/l output stages to transfer this input signal to the can bus lines. enabling sequence the can transceiver requires an enabling time t can,en before a message can be sent on the bus. this means that the txdcan signal can only be pulled low after the enab ling time. if this is not ensured, then the txdcan needs to be set back to high (=recessive) until the enabling time is completed. only the next dominant bit will be transmitted on the bus. figure 21 shows different scenarios and explanations for can enabling. figure 21 can transceiver enabling sequence reduced electromagnetic emission to reduce electromagnetic emissions (eme), the bu s driver controls canh/l slopes symmetrically. reception analog can bus signals are converted into digital si gnals at rxd via the differential input receiver. t v candi f f t can ,en t v txdcan t can m ode can no rmal can off can, en t recessive txd level requir ed bevor start of tr ansmission t can, en not ensured , no tr ansmission on bus can, en t correct sequence , bus is enabled after t can, en t can, en not ensured , no transm ission on bus recessive txd level required dominant recessive
data sheet 55 rev. 1.1, 2014-10-23 TLE9260QXV33 high speed can transceiver 9.2.3 can receive only mode in can receive only mode (rxd only), the driver stage is de-act ivated but reception is still operational. this mode is accessible by an spi command in normal mode a nd in stop mode. the bus biasing is set to vcan/2. 9.2.4 can wake capable mode this mode can be used in sbc stop, sl eep, restart and normal mode and it is used to monitor bus activities. it is automatically accessed in sbc fail-safe mode. both bus pins canh/l are connected to gnd via the input resistors. a wake-up signal on the bus results in a change of behavior of the sbc, as described in table 12 . the pins canh/l are terminated to typ. 2.5v through the input resist ors. as a wake-up signalization to the microcontroller, the rxd_can pin is set low and will stay low until the ca n transceiver is changed to any other mo de. after a wake-up event, the transceiver can be switched to can normal mode for communication via spi. as shown in figure 22 , a wake-up pattern is signaled on the bus by two consecutive dominant bus levels for at least t wake1 (filter time t > t wake1 ), each separated by a recessive bus level of less than t wake2 . figure 22 wup detection following the definition in iso 11898-5 ini bias off 1 bias off 2 bias off 3 bias on 4 bias on wait bias off bus recessive > t wake1 bus dominant > t wake 1 optional: t wake2 expired bus recessive > t wake 1 bus dominant > t wake 1 bus recessive > t wake1 bus dominant > t wake1 optional: t wake 2 expired t silence expired and device in low-power mode t silence expired and device in low-power mode entering can normal or can recive only entering low -power mode , when selective wake-up function is disabled or not supported
data sheet 56 rev. 1.1, 2014-10-23 TLE9260QXV33 high speed can transceiver rearming the transceiver for wake capability after a bus wake-up event, the tran sceiver is woken. however, the can transceiver mode bits will still show wake capable (=?01?) so that the rxd sign al will be pulled low. th ere are two possibilities ho w the can transceiver?s wake capable mode is enabled again after a wake event: ? the can transceiver mode must be toggled, i.e. s witched from wake capable mode to can normal mode, can receive only mode or ca n off, before switching to can wake capable mode again. ? rearming is done automatically when the sbc is ch anged to sbc stop, sbc sleep, or sbc fail-safe mode to ensure wake -up capability. note: it is not necessary to clear the can wake-up bit can_wu to become wake capable aga in. it is sufficient to toggle the can mode. note: the can module is supplied by an internal voltage when in can wake capable mode, i.e. the module must not be supplied through the vcan pin during this time. before changing the can mode to normal mode, the supply of vcan has to be activated first. wake-up in sbc stop and normal mode in sbc stop mode, if a wake-up is detected, it is always signaled by the int output and in the wk_stat_1 spi register. it is also signaled by rxdcan pulled to low. the same applies for the sbc normal mode. the microcontroller should set the device from sbc stop mode to sbc normal mode, there is no automatic transition to normal mode. for functional safety reasons, the watchdog will be automatically enabled in sbc stop mode after a bus wake event in case it was disabled before (if bit wd_en_ wk_bus was configured to high before). wake-up in sbc sleep mode wake-up is possible via a ca n message (filter time t > t wake1 ). the wake-up automatically transfers the sbc into the sbc restart mode and from there to normal mode the corresponding rxd pin in set to low. the microcontroller is able to detect the low signal on rxd and to read the wake source out of the wk_stat_1 register via spi. no interrupt is generated when comi ng out of sleep mode. the microcontroller can now for example switch the can transceiver into can normal mode via spi to start communication. table 12 action due to can bus wake-up sbc mode sbc mode after wake vcc1 int rxd normal mode normal mode on low low stop mode stop mode on low low sleep mode restart mode ramping up high low restart mode restart mode on high low fail-safe mode restart mode ramping up high low
data sheet 57 rev. 1.1, 2014-10-23 TLE9260QXV33 high speed can transceiver 9.2.5 txd time-out feature if the txd signal is dominant for a time t > t txd_can_to , in can normal mode, the txd time-out function deactivates the transmission of the signal at the bus. this is impl emented to prevent the bus from being blocked permanently due to an error. the transmitter is disabled and the tran sceiver is switched to receiv e only mode. the failure is stored in the spi flag can_fail . the can transmitter stage is activated again after the dominant time-out condition is removed and the transceiver is automatica lly switched back to can normal mode.the transceiver configuration stays unchanged. 9.2.6 bus dominant clamping if the hs can bus signal is dominant for a time t > t bus_can_to , regardless of the can transceiver mode a bus dominant clamping is detected and the spi bit can_fail is set. the transceiver configuration stays unchanged. 9.2.7 under voltage detection the voltage at the can supply pin is monitored in can normal mode only. in case of vcan under voltage a signalization via spi bit vcan_uv is triggered and the sbc disables th e transmitter stage. if the can supply reaches a higher level than the under voltage detection threshold (vcan > vcan_uv ), the transceiver is automatically switched back to can normal mode . the transceiver configuration stays unchanged.
data sheet 58 rev. 1.1, 2014-10-23 TLE9260QXV33 high speed can transceiver 9.3 electrical characteristics table 13 electrical characteristics v s = 5.5 v to 28 v; t j = -40 c to +150 c; 4.75 v < v can < 5.25 v; r l = 60 ? ; can normal mode; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. can bus receiver differential receiver threshold voltage, recessive to dominant edge v diff,rd_n ?0.800.90v v diff = v canh - v canl ; -12v v cm (can) +12 v; can normal mode p_10.3.2 differential receiver threshold voltage, dominant to recessive edge v diff,dr_n 0.50 0.60 ? v v diff = v canh - v canl ; -12v v cm (can) +12 v; can normal mode p_10.3.3 common mode range cmr -12 ? 12 v 1) p_10.3.4 canh, canl input resistance r in 20 40 50 k ? can normal / wake capable mode; recessive state p_10.3.6 differential in put resistance r diff 40 80 100 k ? can normal / wake capable mode; recessive state p_10.3.7 input resistance deviation between canh and canl ? r i -3 ? 3 % 1) recessive state p_10.3.38 input capacitance canh, canl versus gnd c in ?2040pf 1) vtxd = 5v p_10.3.39 differential input capacitance c diff ?1020pf 1) vtxd = 5v p_10.3.40 wake-up receiver threshold voltage, recessive to dominant edge v diff, rd_w ? 0.8 1.15 v -12v v cm (can) +12 v; can wake capable mode p_10.3.8 wake-up receiver threshold voltage, dominant to recessive edge v diff, dr_w 0.4 0.7 ? v -12v v cm (can) +12 v; can wake capable mode p_10.3.9
data sheet 59 rev. 1.1, 2014-10-23 TLE9260QXV33 high speed can transceiver can bus transmitter canh/canl recessive output voltage (can normal mode) v canl/h_nm 2.0 ? 3.0 v can normal mode; v txd = v cc1 ; no load p_10.3.11 canh/canl recessive output voltage (can wake capable mode) v canl/h_lp -0.1 ? 0.1 v can wake capable mode; v txd = v cc1 ; no load p_10.3.43 canh, canl recessive output voltage difference v diff = v canh - v canl (can normal mode) v diff_r_n -500 ? 50 mv can normal mode v txd = v cc1 ; no load p_10.3.12 canh, canl recessive output voltage difference v diff = v canh - v canl (can wake capable mode) v diff_r_w -500 ? 50 mv can wake capable mode; v txd = v cc1 ; no load p_10.3.41 canl dominant output voltage v canl 0.5 ? 2.25 v can normal mode; v txd = 0 v; v can = 5 v; 50 ? r l 65 ? p_10.3.13 canh dominant output voltage v canh 2.75 ? 4.5 v can normal mode; v txd = 0 v; v can = 5 v; 50 ? r l 65 ? p_10.3.14 canh, canl dominant output voltage difference v diff = v canh - v canl v diff_d_n 1.5 ? 3.0 v can normal mode; v txd = 0 v; v can = 5 v; 50 ? r l 65 ? p_10.3.16 driver symmetry v sym = v canh + v canl v sym 4.5 ? 5.5 v 2) can normal mode; v txd = 0 v / 5 v; v can = 5 v; c split = 4.7nf; 50 ? r l 60 ? p_10.3.42 canh short circuit current i canhsc -100 -80 -50 ma can normal mode; v canhshort = 0 v p_10.3.17 table 13 electrical characteristics (cont?d) v s = 5.5 v to 28 v; t j = -40 c to +150 c; 4.75 v < v can < 5.25 v; r l = 60 ? ; can normal mode; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
data sheet 60 rev. 1.1, 2014-10-23 TLE9260QXV33 high speed can transceiver canl short circuit current i canlsc 50 80 100 ma can normal mode v canlshort = 18 v p_10.3.18 leakage current (unpowered device) i canh,lk i canl,lk ?57.5a v s = v can = 0v; 0v < v canh,l 5v; 3) r test = 0 / 47 k p_10.3.19 receiver output rxd high level output voltage v rxd,h 0.8 v cc1 ??vcan normal mode i rxd(can) = -2 ma; p_10.3.21 low level output voltage v rxd,l ? ? 0.2 v cc1 vcan normal mode i rxd(can) = 2 ma; p_10.3.22 transmission input txd high level input voltage threshold v txd,h ? ? 0.7 v cc1 vcan normal mode recessive state p_10.3.23 low level input voltage threshold v txd,l 0.3 v cc1 ??vcan normal mode dominant state p_10.3.24 txd input hysteresis v txd,hys ? 0.12 v cc1 ?mv 1) p_10.3.25 txd pull-up resistance r txd 20 40 80 k ? ? p_10.3.26 can transceiver enabling time t can,en ?10?s 4) csn = high to first valid transmitted txd dominant p_10.3.27 dynamic can-transceiver characteristics min. dominant time for bus wake-up t wake1 0.50 ? 3 s -12v v cm (can) +12 v; can wake capable mode p_10.3.28 wake-up time-out, recessive bus t wake2 0.5 ? 10 ms 4) can wake capable mode p_10.3.29 wup wake-up reaction time t wu_wup ??100s 4)5)6) wake-up reaction time after a valid wup on can bus; p_10.3.44 table 13 electrical characteristics (cont?d) v s = 5.5 v to 28 v; t j = -40 c to +150 c; 4.75 v < v can < 5.25 v; r l = 60 ? ; can normal mode; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
data sheet 61 rev. 1.1, 2014-10-23 TLE9260QXV33 high speed can transceiver propagation delay txd-to-rxd low (recessive to dominant) t d(l),tr ? 150 255 ns 2) can normal mode c l = 100 pf; r l = 60 ? ; v can = 5 v; c rxd = 15 pf p_10.3.30 propagation delay txd-to-rxd high (dominant to recessive) t d(h),tr ? 150 255 ns 2) can normal mode c l = 100 pf; r l = 60 ? ; v can = 5 v; c rxd = 15 pf p_10.3.31 propagation delay txd low to bus dominant t d(l),t ? 50 ? ns can normal mode c l = 100pf; r l = 60 ? ; v can = 5 v; p_10.3.32 propagation delay txd high to bus recessive t d(h),t ? 50 ? ns can normal mode c l = 100 pf; r l = 60 ? ; v can = 5 v; p_10.3.33 propagation delay bus dominant to rxd low t d(l),r ? 100 ? ns can normal mode c l = 100pf; r l = 60 ? ; v can = 5 v; c rxd = 15 pf p_10.3.34 propagation delay bus recessive to rxd high t d(h),r ? 100 ? ns can normal mode c l = 100pf; r l = 60 ? v can = 5 v; c rxd = 15 pf p_10.3.35 recessive bit width on rxd (can fd up to 2mbps) t bit(rxd) 400? 550nscan normal mode c l = 100pf; r l = 60 ? ; v can = 5 v; c rxd = 15 pf; t bit(txd) = 500ns; refer to figure 24 p_10.3.46 table 13 electrical characteristics (cont?d) v s = 5.5 v to 28 v; t j = -40 c to +150 c; 4.75 v < v can < 5.25 v; r l = 60 ? ; can normal mode; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
data sheet 62 rev. 1.1, 2014-10-23 TLE9260QXV33 high speed can transceiver figure 23 timing diagrams for dynamic characteristics txd permanent dominant time-out t txd_can_to ?2?ms 4) can normal mode p_10.3.36 bus permanent dominant time-out t bus_can_to ?2?ms 4) can normal mode p_10.3.37 1) not subject to production test, specified by design. 2) f txd = 250 khz rectangular signal, duty cycle = 50%; 3) rtest between supply (vs / vcan) and 0v (gnd); 4) not subject to production test, tolerance defined by internal oscillator tolerance; 5) wake-up is signalized via int pin activation in sbc stop mo de and via vcc1 ramping up with wake from sbc sleep mode; 6) time starts with end of last dominant phase of wup; table 13 electrical characteristics (cont?d) v s = 5.5 v to 28 v; t j = -40 c to +150 c; 4.75 v < v can < 5.25 v; r l = 60 ? ; can normal mode; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. t d(l), r t v di f f t d(l), t r t d(h), r t d(h),tr t d(l ),t t gnd v txd v cc 1 t d(h), t v dif f , rd_n v diff, dr_n t gnd 0.2 x v cc1 0.8 x v cc 1 v rxd v cc 1 can dynamic characteristics.vsd
data sheet 63 rev. 1.1, 2014-10-23 TLE9260QXV33 high speed can transceiver figure 24 timing diagrams for rxd recessive bit width definition t bit(rxd)
data sheet 64 rev. 1.1, 2014-10-23 TLE9260QXV33 wake and voltage monitoring inputs 10 wake and voltage monitoring inputs 10.1 block description figure 25 wake input block diagram features ? three high-voltage inputs with a 3v (typ.) threshold voltage ? alternate measurement function for high-voltage sensing via wk1 and wk2 ? wake-up capability fo r power saving modes ? edge sensitive wake feature low to high and high to low ? pull-up and pull-down current sources, configurable via spi ? selectable configuration for static sense or cyclic sense working with timer1, timer2 ? in sbc normal and sbc stop mode the level of the wk pi n can be read via spi even if the respective wk is not enabled as a wake source. monx_input_circuit_ext.vsd + - t wk wkx internal supply logic i pd_wk i pu_wk v ref
data sheet 65 rev. 1.1, 2014-10-23 TLE9260QXV33 wake and voltage monitoring inputs 10.2 functional description the wake input pins are edge-sensitive inputs with a switching threshold of typically 3v. this means that both transitions, high to low and low to high, result in a signalization by the sbc. the signalization occurs either in triggering the interrupt in sbc normal mode and sbc stop mode or by a wake up of the device in sbc sleep and sbc fail-safe mode. two different wake detection modes can be selected via spi: ? static sense: wk inputs are always active ? cyclic sense: wk inputs are only ac tive for a certain time period (see chapter 5.2.1 ) two different filter times of 16s or 64s can be select ed to avoid a parasitic wake-up due to transients or emc disturbances in static sense configuration. the filter time ( t fwk1 , t fwk2 ) is triggered by a level change crossing the switching threshold and a wake signal is recognized if the input level will not cross again the threshold du ring the selected filter time. figure 26 shows a typical wake-up timing and parasitic filter. figure 26 wake-up filter timing for static sense the wake-up capability for each wk pin can be enabled or disabled vi a spi command in the wk_ctrl_2 register. the wake source for a wake via a wkx pin can always be read in the register wk_stat_1 at the bits wk1_wu, wk2_wu, and wk3_wu. the actual voltage level of the wk pin (low or high ) can always be read in sbc normal and sbc stop mode in the register wk_lvl_stat . during cyclic sense, the register show the sampled levels of the respective wk pin. if fo2...3 are configured as wk inputs in its alternative function (16s static filter time), then the wake events will be signalled in the register wk_stat_2 . v wk,th t v wk t wk,f no wake event wake event v wk,th t wk,f t v int t int
data sheet 66 rev. 1.1, 2014-10-23 TLE9260QXV33 wake and voltage monitoring inputs 10.2.1 wake input configuration to ensure a defined and stable voltage levels at the intern al comparator input it is po ssible to configure integrated current sources via the spi register wk_pupd_ctrl . in addition, the wake detection modes (including the filter time) can be configured via the spi register wk_flt_ctrl . an example illustration fo r the automatic switching configuration is shown in figure 27 . note: if there is no pull-up or pull-down configured on th e wk input, then the respective input should be tied to gnd or vs on board to avoid unintended floating of the pin and subsequent wake events. figure 27 illustration for pull-up / down current sources with automatic switching configuration config a and b are intended for static sense with two differ ent filter times. config c or d are intended for cyclic se nse configuration. with the filter se ttings, the respective timer needs to be assigned to one or more hs output, which supplies an external circuit connected to the wkx pin, e.g. hs1 controlled by timer 2 (hs1 = 010) and connected to wk3 via an switch circuitry - see also chapter 5.2 . table 14 pull-up / pull-down resistor wkx_pupd _1 wkx_pupd _0 current sources note 0 0 no current source wkx input is fl oating if left open (default setting) 0 1 pull-down wkx input inte rnally pulled to gnd 1 0 pull-up wkx input internally pulled to internal 5v supply 1 1 automatic switching if a high level is detected at the wkx input the pull-up source is activated, if low level is dete cted the pull down is activated. table 15 wake detection configuration and filter time wkx_flt_1 wkx_flt_0 filter time description 0 0 config a static sense, 16s filter time 0 1 config b static sense, 64s filter time 1 0 config c cyclic sense, timer 1, 16s filter time. period, on-time configurable in register timer1_ctrl 1 1 config d cyclic sense, timer 2, 16s filter time. period, on-time configurable in register timer2_ctrl i wk i wkth _min i wkth _max v wkth
data sheet 67 rev. 1.1, 2014-10-23 TLE9260QXV33 wake and voltage monitoring inputs 10.2.2 alternate measurement function with wk1 and wk2 10.2.2.1 block description this function provides the possibility to measure a volta ge, e.g. the unbuffered battery voltage, with the protected wk1 hv-input. the measured voltage is routed out at wk 2. it allows for example a voltage compensation for led lighting by changing the duty cycle of the high-side output s. a simple voltage divider needs to be placed externally to provide the correct voltage level to the microcontroller a/d converter input. the function is available in sbc normal mode and it is disabled in all other modes to allow a low-quiescent current operation.the meas urement function can be used instead of the wk1 and wk2 wake and level signalling capability. the benefits of the function is that the signal is meas ured by a hv-input pin and that there is no current flowing through the resistor divider during low-power modes. the functionality is shown in a simplified applicat ion diagram in figure 48 . 10.2.2.2 functional description this measurement function is by default disabled. in this case, wk1 and wk2 have the regular wake and voltage level signalization functionality. the switch s1 is open for this configuration (see figure 48 ). the measurement function can be enabled via the spi bit wk_meas . if wk_meas is set to ?1?, then the measurement function is enabled and switch s1 is closed in sbc normal mode. s1 is open in all other sbc modes. if this function th e pull-up and down currents of wk1 and wk2 are disabled, and the internal wk1 and wk2 signals are gated. in ad dition, the settings for wk1 and wk2 in the registers wk_pupd_ctrl , wk_flt_ctrl and wk_ctrl_2 are ignored but changing these setting is not prevented. the registers wk_stat_1 and wk_lvl_stat are not updated with respect to the inputs wk1 and wk2. however, if only wk1 or wk2 are set as wake sources and a sbc sleep mode command is set, then the spi_fail flag will be set and the sbc will be ch anged into sbc re start mode (see chapter 5.1 also for wake capability of wk1 and wk2). note: there is a diode in series to the switch s1 (not shown in the figure 48 ), which will influe nce the temperature behavior of the switch. table 16 differences between normal wk function and measurement function affected settings/modules for wk1 and wk2 inputs wk_meas = 0 wk_meas = 1 s1 configuration ?open? ?closed? in sbc normal mode, ?open? in all other sbc modes internal wk1 & wk2 signal processing default wake and level signaling function, wk_stat_1 , wk_stat_2 are updated accordingly ?wk1...2 inputs are gated internally, wk_stat_1 , wk_stat_2 are not updated wk1_en , wk2_en wake-up via wk1 and wk2 possible if bits are set setting the bits is ignored and not prevented. if only wk1_en , wk2_en are set while trying to go to sbc sleep mode, then the spi_fail flag will be set and the sbc will be changed into sbc restart mode. wk_pupd_ctrl normal configuration is possible no pull-up or pull-down enabled wk_flt_ctrl normal configuration is possible setti ng the bits is ignored and not prevented
data sheet 68 rev. 1.1, 2014-10-23 TLE9260QXV33 wake and voltage monitoring inputs 10.3 electrical characteristics table 17 electrical characteristics v s = 5.5 v to 28 v; t j = -40 c to +150 c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. wk1...wk3 input pin characteristics wake-up/monitoring threshold voltage v wkth 2 3 4 v without external serial resistor r s (with r s : ? v = i pd/pu * r s ); hysteresis included p_12.3.1 threshold hysteresis v wknth,hys 0.1 - 0.7 v without external serial resistor r s (with r s : ? v = i pd/pu * r s ); p_12.3.2 wk pin pull-up current i pu_wk -20 -10 -3 a v wk_in = 4v p_12.3.3 wk pin pull-down current i pd_wk 31020a v wk_in = 2v p_12.3.4 input leakage current i lk,l -2 2 a 0 v < v wk_in < 40v p_12.3.5 drop voltage across s1 switch v drop,s1 ? 1000 ? mv 1) drop voltage between wk1 and wk2 when enabled for voltage measurement; i wk1 = 500a; t j = 25c refer to figure 28 1) not subject to production test; specified by design p_12.3.13 timing wake-up filter time 1 t fwk1 -16-s 2) spi setting 2) not subject to production test, tolerance defined by internal oscillator tolerance p_12.3.6 wake-up filter time 2 t fwk2 -64-s 2) spi setting p_12.3.7
data sheet 69 rev. 1.1, 2014-10-23 TLE9260QXV33 wake and voltage monitoring inputs figure 28 typical drop voltage characteristics of s1 (between wk1 & wk2) 800 900 1000 1100 a gedropofswitchs1(mv) vs = 13.5v 250 a 500 a 500 600 700 50 0 50 100 150 v s1 ,volt a tj junctiontemperature(c) 50 a 100 a
data sheet 70 rev. 1.1, 2014-10-23 TLE9260QXV33 interrupt function 11 interrupt function 11.1 block and functional description figure 29 interrupt block diagram the interrupt is used to signalize special events in real time to the microcontroller. the interrupt block is designed as a push/pull output stage as shown in figure 29 . an interrupt is triggered and the int pin is pulled low (active low) for t int in sbc normal and stop mode and it is released again once t int is expired. the minimum high-time of int between two consecutive interrupts is t intd . an interrupt does not cause a sbc mode change. two different interrupt classes could be selected via the spi bit int_ global : ? class 1 (wake interrupt - int_ global =0): all wake-up events stored in the wake status spi register ( wk_stat_1 and wk_stat_2 ) cause an interrupt (default setting). an interrupt is only triggered if the respective function is also enabled as a wake sour ce (including gpiox if configured as a wake input). ? class 2 (global interrupt - int_ global =1): in addition to the wake-up events, all signalled failures stored in the other status registers caus e an interrupt (the register wk_lvl_stat is not generating interrupts) note: the errors which will cause sbc restart or sbc fail-safe mode (v cc1_uv, wd_fail, vcc1_sc, tsd2, failure) are the exceptions of an int generation on status bits. al so por and dev_stat_x and will not generate interrupts. in addition to this behavior, an int will be triggered when the sbc is sent to sbc stop mode and not all bits were cleared in the wk_stat_1 and wk_stat_2 register. the spi status registers are updated at every falling edge of the int pulse. all interrup t events are st ored in the respective register (except the register wk_lvl_stat ) until the register is read and cleared via spi command. a second spi read after reading out the respective status register is optional but recommended to verify that the interrupt event is not present anymore. the interrupt behavior is shown in figure 30 for class 1 interrupts. the behavior for class 2 is identical. the int pin is also used during sbc init mode to se lect the hardware configuration of the device. see chapter 5.1.1 for further information. interrupt logic int time out v cc1
data sheet 71 rev. 1.1, 2014-10-23 TLE9260QXV33 interrupt function figure 30 interrupt signalization behavior interrupt_behavior.vsd int wk1 wk2 t int t intd update of wk_stat register spi read & clear update of wk_stat register wk_stat contents scenario 1 wk1 no wk wk2 no wk optional spi read & clear wk_stat contents scenario 2 wk1 + wk2 no wk no spi read & clear command sent
data sheet 72 rev. 1.1, 2014-10-23 TLE9260QXV33 interrupt function 11.2 electrical characteristics table 18 interrupt output v s = 5.5 v to 28 v; t j = -40 c to +150 c; sbc normal mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. parameter symbol values unit note / test condition number min. typ. max. interrupt output; pin int int high output voltage v int,h 0.8 v cc1 ??v 1) i int = -1 ma; int = off 1) output voltage value also determines device configuration during sbc init mode p_13.2.1 int low output voltage v int,l ? ? 0.2 v cc1 v 1) i int = 1 ma; int = on p_13.2.2 int pulse width t int ?100?s 2) 2) not subject to production test, tolerance defined by internal oscillator tolerance. p_13.2.3 int pulse minimum delay time t intd ?100?s 2) between consecutive pulses p_13.2.4 configuration select; pin int config pull-down resistance r cfg ?250?k ? v int = 3.3 v p_13.2.5 config select filter time t cfg_f ?7 ?s 2) p_13.2.6
data sheet 73 rev. 1.1, 2014-10-23 TLE9260QXV33 fail outputs 12 fail outputs 12.1 block and functional description figure 31 simplified fail output block diagram for fo1/2 and for fo3/test the fail outputs consist of a failure logic block and three open-drain outputs (fo1, fo2, fo3) with active-low signalization. the fail outputs are activated due to following failure conditions: ? watchdog trigger failure (for config 3&4 only after the 2nd watchdog trigger failure and for config 1&2 after 1st watchdog trigger failure) ? thermal shutdown tsd2 ? vcc1 short to gnd ? vcc1 over voltage (only if the spi bit vcc1_ov_rst is set) ? after 4 consecutive vcc1 under voltage event (see chapter 13.6 for details) at the same time sbc fail-safe mode is entered (excep tions are watchdog trigger failures depending on selected configurations - see chapter 5.1.1 ). the fail output activation is signalled in the spi bit failure of the register dev_stat . for testing purposes only the fail outputs can also be activated via spi by setting the bit fo_on . this bit is independent of the fo failure bits. in ca se that there is no failure condition, the fo outputs can also be turned off again via spi, i.e. no successful watchdog trigger is needed. the entry of sbc fail-safe mode due to a watchdog failure can be configured as described in chapter 5.1.1 . in order to deactivate the fail outputs in sbc normal mode the failure conditions must not be present anymore (e.g. tsd2, vcc1 short circuit, etc) and the bit failure needs to be cleared via spi command. in case of a failure bit setting due to a watchdog fail, a success ful wd trigger is needed in addition, i.e. wd_fail must be cleared. wd_fail will also be cleared when going to sbc sleep or sbc fail-safe mode due to another failure (not a wd failure) or if the watchd og is disabled in sbc stop mode. note: the fail output pin is triggered for any of the abov e described failures. no fail ure is caused for the 1st watchdog failure if selected for config2. the three fail outputs are activated simultaneou sly with following outp ut functionalities: ? fo1: static fail output ? fo2: 1.25hz, 50% (typ.) duty cycle, e.g. to generate an indicator signal failure logic fo1/2 fo3/test 5v_int r test sbc init mode failure logic t test t fo_pl
data sheet 74 rev. 1.1, 2014-10-23 TLE9260QXV33 fail outputs ? fo3: 100hz pwm, 20% (typ.) duty cycle, e.g. to generate a dimmed rear light from a break light. note: the duty cycle for fo3 can be configured via spi option to 20%, 10%, 5% or 2.5%. default value is 20%. see the register fo_dc for configuration. 12.1.1 general purpose i/o functionality of fo2 and fo3 as alte rnate function in case that fo2 and fo3 are not used in the application, those pins can also be configured with an alternate function as high-voltage (vshs related) general purpose i/o pins. figure 32 simplified general purpose i/o block diagram for fo2 and fo3/test the pins are by default configured as fo pins. the configuration is done via the spi register gpio_ctrl . the alternate function can be: ? wake inputs: the detection threshold v gpioi,th is similar as for the wk inputs. the wake-up detection behavior is the same as for wkx pins. wake events are stored and reported in wk_stat_2 . ? low-side switches: the switch is able to drive currents of up to 10ma (see also v gpiol,l1 ). it is self-protected with regards to current limitation. no other diagnosis is implemented. ? high-side switches: the switch is able to drive currents up to 10ma (see also v gpioh,h1 ). it is self-protected with regards to current lim itation. no other diagnosis is implemented. ? if configured as gpio then the resp ective level at the pin will be shown in wk_lvl_stat in sbc normal and stop mode. this is also the case if configured as ls/hs and can serve as a feedback about the respective state. gpio2 is shared with the test level bit. figure 33 describes the behavior of the fo/gpio pins in their different configurations and sbc modes. figure 33 fo / gpio behavior for the respective sbc modes note: in order to avoid unintentional entry of sbc deve lopment mode care must be taken that the level of fo3/test is high during device power up and sbc init mode. note: the fox drivers are supplied via vs. however, the gpio hs switches (fo2, fo3/test) are supplied by vshs config & control logic fox/ gpiox vshs function normal mode stop mode sleep mode fail-safe mode fox keeps the state keeps the state active wk wake capable wake capable off hs as configured in normal mode off off ls as configured in normal mode off off configurable
data sheet 75 rev. 1.1, 2014-10-23 TLE9260QXV33 fail outputs 12.2 electrical characteristics table 19 interrupt output v shs = 5.5 v to 28 v; t j = -40 c to +150 c; sbc normal mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. 1) 1) the fox drivers are supplied via vs. however, the gp io hs switches (fo2, fo3/test) are supplied by vshs parameter symbol va lues unit note / test condition number min. typ. max. pin fo1 fo1 low output voltage (active) v fo,l1 ?? 1.0v i fo = 4ma p_14.2.1 fo1 high output current (inactive) i fo,h 0? 2a v fo = 28v p_14.2.2 pin fo2 fo2 side indicator frequency f fo2si 1.00 1.25 1.50 hz 3) p_14.2.3 fo2 side indicator duty cycle d fo2si ?50?% 3) p_14.2.4 pin fo3/test 2) pull-up resistance at pin fo3/test r test 2.5 5 10 k ? v test =0v; sbc init mode p_14.2.5 test input filter time t test ?64?s 3) p_14.2.6 fo3 pulsed light frequency f fo3pl 80 100 120 hz 3) p_14.2.7 fo3 pulsed light duty cycle d fo3pl ?20?% 3)4) default setting p_14.2.8 alternate fo2...3 electrical characteristics: gpio gpio low-side output voltage (active) v gpiol,l1 ?? 1v i gpio = 10ma p_14.2.9 gpio low-side output voltage (active) v gpiol,l2 ?? 5mv 5) i gpio = 50a p_14.2.17 gpio high-side output voltage (active) v gpioh,h1 vshs-1 ? ? v i gpo = -10ma p_14.2.10 gpio high-side output voltage (active) v gpioh,h2 vshs-5 ? ? mv 5) i gpo = -50a p_14.2.18 gpio input threshold voltage v gpioi,th 1.5 2.5 3.5 v 6) hysteresis included p_14.2.11 gpio input threshold hysteresis v gpioi,hys 100 400 700 mv 5) p_14.2.12 gpio low-side current limitation i gpiol,max 10 ? 30 ma v gpio = 28v p_14.2.13 gpio high-side current limitation i gpioh,max -45 ? -10 ma v gpio = 0v p_14.2.14
data sheet 76 rev. 1.1, 2014-10-23 TLE9260QXV33 fail outputs 2) the external capacitance on this pin must be limited to le ss than 10nf to ensure proper detection of sbc development mode and sbc user mode operation. 3) not subject to production test, tolerance defined by internal oscillator tolerance. 4) the duty cyclic is adjustable via the spi bits fo_dc . 5) not subject to production test, specified by design. 6) applies also for test voltage input level
data sheet 77 rev. 1.1, 2014-10-23 TLE9260QXV33 supervision functions 13 supervision functions 13.1 reset function figure 34 reset block diagram 13.1.1 reset output description the reset output pin ro provides a reset information to the microcontroller, for example, in the event that the output voltage has fallen below the under voltage threshold v rt1/2/3/4 . in case of a reset ev ent, the reset output ro is pulled to low afte r the filter time t rf and stays low as long as the reset ev ent is present plus a reset delay time t rd1 . when connecting the sbc to battery voltage, the rese t signal remains low initia lly. when the output voltage v cc1 has reached the reset default threshold v rt1,r , the reset output ro is released to high after the reset delay time t rd1 . a reset can also occur due to a watchdog trigger failure. the reset threshold can be adjusted via spi, the default reset threshold is v rt1,f . the ro pin has an integrat ed pull-up resistor. in case reset is triggered, it will be pulled low for v cc1 1v and for vs v por,f (see also chapter 13.3 ). the timings for the ro triggering regarding vcc1 under voltage and watchdog trigger is shown in figure 35 . reset logic incl. filter & delay ro v c c 1
data sheet 78 rev. 1.1, 2014-10-23 TLE9260QXV33 supervision functions figure 35 reset timing diagram 13.1.2 soft reset description in sbc normal and sbc stop mode, it is also possible to trigger a device internal reset via a spi command in order to bring the sbc into a defined state in case of fa ilures. in this case the mi crocontroller must send a spi command and set the mode bits to ?11? in the m_s_ctrl register. as soon as this command becomes valid, the sbc is set back to sbc init mode and all spi registers are set to their default values (see spi chapter 14.5 and chapter 14.6 ). two different soft reset configurations are possible via the spi bit soft_ reset_ro : ? the reset output (ro) is triggered wh en the soft reset is executed (default setting, the same reset delay time t rd1 applies) ? the reset output (ro) is not triggered when the soft reset is executed note: the device must be in sbc normal mode or sbc stop mode when sending this command. otherwise, the command will be ignored. the reset threshold can be configured via spi in sbc normal mode , default is v rt 1 t rd1 t lw sbc init ro spi t vcc v rt1 undervoltage t rd1 sbc normal t t t lw t < t rf t rf t cw sbc restart sbc normal spi init t cw t ow wd trigger t cw t ow wd trigger spi init t lw = long open window t cw = closed window t ow = open window
data sheet 79 rev. 1.1, 2014-10-23 TLE9260QXV33 supervision functions 13.2 watchdog function the watchdog is used to monitor the software execution of the microcontroller and to trigger a reset if the microcontroller stops serving the watchdog due to a lock up in the software. two different types of watchdog functions are implemented and can be selected via the bit wd_win : ? time-out watchdog (default value) ? window watchdog the respective watchdog functions can be selected and programmed in sbc normal mode. the configuration stays unchanged in sbc stop mode. please refer to table 20 to match the sbc modes with the respective watchdog modes. the watchdog timing is programmed via spi command. as soon as the watch dog is programmed, the timer starts with the new setting and the watchdog must be served. the watchdog is triggered by sending a valid spi-write command to the watchdog configuration register. the trigger spi command is executed when the chip select input (csn) becomes high. when coming from sbc init, sbc restart mode or in ce rtain cases from sbc stop mode, the watchdog timer is always started with a long open window. the long open window ( t lw = 200ms) allows the mi crocontroller to run its initialization sequences and then to trigger the watchdog via spi. the watchdog timer period can be sele cted via the watchdog timing bit field ( wd_timer ) and is in the range of 10 ms to 1000 ms. this setting is valid for both watchdog types. the following watchdog timer periods are available: ? wd setting 1: 10ms ? wd setting 2: 20ms ? wd setting 3: 50ms ? wd setting 4: 100ms ? wd setting 5: 200ms ? wd setting 6: 500ms ? wd setting 7: 1000ms in case of a watchdog reset, sbc restart or sbc fail- safe mode is entered according to the configuration and the spi bits wd_fail are set. once the ro goes high again the watchdog immediately starts with a long open window the sbc enters automa tically sbc normal mode. in sbc software development mode the watchdog is off and therefore no reset and interrupt are generated due to a watchdog failure. table 20 watchdog functionality by sbc modes sbc mode watchdog mode remarks init mode starts with long open window watchdog starts with long open window after ro is released normal mode wd programmable window watchdog, time-out watchdog or switched off for sbc stop mode stop mode watchdog is fixed or off sleep mode off sbc will start with lon g open window when entering sbc normal mode. restart mode off sbc will start with long open window when entering sbc normal mode.
data sheet 80 rev. 1.1, 2014-10-23 TLE9260QXV33 supervision functions depending on the configuration, the wd_fail bits will be set after a watchdo g trigger failure as follows: ? in case an incorrect wd trigger is received (triggerin g in the closed watchdog window or when the watchdog counter expires without a valid trigger) then the wd_fail bits will be increased (showing the number of incorrect wd triggers) ? for config 2: the bits can have the maximum value of ?01? ? for config 1, 3 and 4: the bits can have the maximum value of ?10? the wd_fail bits are cleared automatically when following conditions apply: ? after a successful watchdog trigger ? when the watchdog is off: in sbc stop mode after succ essfully disabling it, in sbc sleep mode, or in sbc fail-safe mode (except for a watchdog failure) 13.2.1 time-out watchdog the time-out watchdog is an easier and less secure wa tchdog than a window watchdog as the watchdog trigger can be done at any time within th e configured watchdog timer period. a correct watchdog service immediately results in starti ng a new watchdog timer period. taking the tolerances of the internal oscillator into account leads to the safe tr igger area as defined in figure 36 . if the time-out watchdog period elapses, a watchdog reset is created by setting the reset output ro low and the sbc switches to sbc restart or sbc fail-safe mode. figure 36 time-out watchdog definitions open window t / [t wd_timer ] safe trigger area wd1_timeout_per.vsd watchdog timer period (wd_timer) uncertainty typical timout watchdog trigger period t wd x 1.80 t wd x 1.20 t wd x 1.50
data sheet 81 rev. 1.1, 2014-10-23 TLE9260QXV33 supervision functions 13.2.2 window watchdog compared to the time-out watchdog the characteristic of the window watc hdog is that the watchdog timer period is divided between an closed and an open window. t he watchdog must be triggered within the open window. a correct watchdog trigger results in starting the windo w watchdog period by a closed window followed by an open window. the watchdog timer period is at the sa me time the typical trigger time and defines the middle of the open window. taking the oscillator tolera nces into account leads to a safe trigger area of: t wd x 0.72 < safe trigger area < t wd x 1.20. the typical closed window is defined to a width of 60% of the selected window watchdog timer period. taking the tolerances of the internal os cillator into account leads to the timings as defined in figure 37 . a correct watchdog service immediately resu lts in starting the next closed window. should the trigger signal meet the closed window or should the watchdog timer period elapse, then a watchdog reset is created by setting the reset output ro low and the sbc switches to sbc rest art or sbc fail-safe mode. figure 37 window watchdog definitions 13.2.3 watchdog setting check sum a check sum bit is part of the spi commend to trig ger the watchdog and to set the watchdog setting. the sum of the 8 data bits in the register wwd_ctrl needs to have even parity (see equation (1) ). this is realized by either setting the bit checksum to 0 or 1. if the check sum is wrong, then the spi command is ignored, i.e. the watchdog is not triggered or the settings are not changed and the bit spi_fail is set. the checksum is calculated by taking all 8 data bits into account. the written value of the reserved bit 3 of the wwd_ctrl register is considered (even if read as ?0? in the sp i output) for checksum calc ulation, i.e. if a 1 is written on the reserved bit position, then a 1 will be used in the checksum calculation. (1) closed window open window t / [t wd_timer ] safe trigger area t wd x 0.72 t wd x 1.20 uncertainty uncertainty t wd x 0.48 t wd x 1.80 watchdog timer period (wd_timer) typ. closed window typ. open window t wd x 0.6 t wd x 1.0 t wd x 0.9 chksum bit15 bit8 =
data sheet 82 rev. 1.1, 2014-10-23 TLE9260QXV33 supervision functions 13.2.4 watchdog durin g sbc stop mode the watchdog can be disabled for sbc stop mode in sbc normal mode. for safety reasons, there is a special sequence to be followed in order to disable the watchdog as described in figure 38 . two different spi bits ( wd_stm_ en_0 , wd_stm_ en_1 ) in the registers wk_ctrl_1 and wd_ctrl need to be set. figure 38 watchdog disabling sequence in sbc stop mode if a sequence error occurs, then the bit wd_stm_ en_1 will be cleared and the sequenc e has to be started again. the watchdog can be enabled by triggering the watchdog in sbc stop mode or by s witching back to sbc normal mode via spi command. in both cases the watchdog will start with a long open win dow and the bits wd_stm_en_1 and wd_stm_ en_0 are cleared. after th e long open window the watchdog has to be served as configured in the wd_ctrl register. note: the bit wd_stm_ en_0 will be cleared automatically when the sequence is star ted and it was 1 before. 13.2.5 watchdog start in sbc st op mode due to bus wake in sbc stop mode the watch dog can be disabled. in addi tion a feature is available which will start the watchdog with any bus wake (can) during sbc stop mode. the feature is enabled by setting the bit wd_en_ wk_bus = 1 (= default value after por). the bit can only be changed in sbc normal mode and needs to be programmed before starting the watchdog disable sequence. a wake on can will generate an interrupt and the rxd pin for can is pulled to low. by these signals the microcontroller is informed that the wa tchdog is startedwith a long open window. after the long open window the watchdog has to be served as configured in the wd_ctrl register. to disable the watchdog again, the sbc needs to be switched to normal mode and the sequence needs to be sent again. correct wd disabling sequence set bit wd_stm_en_1 = 1 set bit wd_stm_en_0 = 1 with next wd trigger wd is switched off sequence errors ? missing to set bit wd_stm_en_0 with the next watchdog trigger after having set wd_stm_en_1 ? staying in normal mode instead of going to stop mode with the next trigger change to sbc stop mode before subsequent wd trigger will enable the wd : ? switching back to sbc normal mode ? triggering the watchdog
data sheet 83 rev. 1.1, 2014-10-23 TLE9260QXV33 supervision functions 13.3 vs power on reset at power up of the device, the vs power on reset is detected when vs > v por,r and the spi bit por is set to indicate that all spi registers are set to por default settings. vcc1 is starting up and the reset output will be kept low and will only be released once vcc1 has crossed v rt1,r and after t rd1 has elapsed. in case vs < v por,f , an device internal reset will be generated and the sbc is switched off and will restart in init mode at the next vs rising. this is shown in figure 39 . figure 39 ramp up / down example of supply voltage t vcc1 t v por,f ro t vs v por,r t rd1 v rt1,r v rtx,f t sbc mode sbc off sbc off sbc init mode any sbc mode spi command the reset threshold can be configured via spi in sbc normal mode , default is v rt1 re- start sbc restart mode is entered whenever the reset is triggered
data sheet 84 rev. 1.1, 2014-10-23 TLE9260QXV33 supervision functions 13.4 under voltage vs and vshs if the supply voltage vs reaches the under voltage threshold v s,uv then the sbc does the following measures: ? spi bit vs_uv is set. no other error bits are set. the bit can be cleared once the condition is not present anymore, ? the vcc1 short circuit protection becomes inactive (see chapter 13.7 ). however, the thermal protection of the device remains active. if the under voltage thresh old is exceeded (vs rising) then functions will be au tomatically enabled again. if the supply voltage vshs passes below the under voltage threshold ( v shs,uvd ) the sbc does the following measures: ? hs1...4 are acting accordingly to the spi setting (see chapter 8 ) ? spi bit vshs_uv is set. no other error bits are set. the bi t can be cleared once the condition is not present anymore, ? vcc1, vcc2, wkx and can are not affected by vshs under voltage 13.5 over voltage vshs if the supply voltage vshs reaches the over voltage threshold ( v shs,ovd ) the sbc triggers the following measures: ? hs1...4 are acting accordingly to the spi setting (see chapter 8 ) ? spi bit vshs_ov is set. no other error bits are set. the bit ca n be cleared once the condition is not present anymore, ? vcc1, vcc2, wkx and can are not affected by vs over voltage 13.6 vcc1 over-/ under voltage and under voltage prewarning 13.6.1 vcc1 under voltage a nd under voltage prewarning a first-level voltage detection threshol d is implemented as a prewarning fo r the microcontroller. the prewarning event is signaled with the bit vcc1_ warn . no other actions are taken. as described in chapter 13.1 and figure 40 , a reset will be triggered (ro pulled ?low?) when the v cc1 output voltage falls below the selected under voltage threshold (v rtx ). the bit vcc1_uv is set and the sbc will enter sbc restart mode. note: the vcc1_ warn or vcc1_uv bits are not set in sleep mode as v cc1 = 0v in this case
data sheet 85 rev. 1.1, 2014-10-23 TLE9260QXV33 supervision functions figure 40 vcc1 under voltage timing diagram an additional safety mechanism is implemented to avoid re petitive vcc1 under voltage resets due to high dynamic loads on vcc1: ? a counter is increased for every consecutive vcc1 under voltage event (regardless on the selected reset threshold), ? the counter is active in sbc init-, normal-, and stop mode, ? for vs < v s,uv the counter will be stoppe d in sbc normal mode (i.e. the vs uv comparator is always enabled in sbc normal mode), ? a 4th consecutive vcc1 u nder voltage event will lead to sbc fail-safe mode entr y and to setting the bit vcc1_uv _fs ? this counter is cleared: ? when sbc fail-safe mode is entered, ? when the bit vcc1_uv is cleared, ? when a soft reset is triggered. note: it is recommended to clear the vcc1_uv bit once it was set and detected. 13.6.2 vcc1 over voltage for fail-safe reasons a configurable vcc1 over voltage detec tion feature is implemented. it is active in sbc init-, normal-, and stop mode. in case the v cc1,ov,r threshold is crossed, the sbc triggers following measures depending on the configuration: ? the bit vcc1_ ov is always set; ? if the bit vcc1_ov_rst is set and cfgp = ?1?, then sbc restart mode is entered. the fox outputs are activated. after the reset delay time ( t rd1 ), the sbc restart mode is left and sbc normal mode is resumed even if the vcc1 over voltage event is still present (see also figure 41 ). the vcc1_ov_rst bit is cleared automatically; ? if the bit vcc1_ov_rst is set and cfgp = ?0?, then sbc fail-safe mode is entered and fox outputs are activated. note: external noise could be coupled into the vcc1 supply line. especially, in case the vcc1 output current in sbc stop mode is below the active peak threshold (i vcc1,ipeak ) the bit vcc1_ov_rst must be set to ?0? before entering sbc stop mode to avoid unintentional sb c restart or fail-safe mode entry and to ignore the vcc1_ ov bit due to external noise. ro t vcc1 v rtx t rd1 sbc normal t t rf sbc restart sbc normal
data sheet 86 rev. 1.1, 2014-10-23 TLE9260QXV33 supervision functions figure 41 vcc1 over voltage timing diagram 13.7 vcc1 short circuit diagnostics the short circuit protection feature for v cc1 is implemented as follows (vs needs to be higher than v s,uv ): ? if vcc1 is not above the v rtx within t vcc1,sc after device power up or after waking from sbc sleep mode then the spi bit vcc1_sc bit is set, vcc1 is turned off, the fox pins are enabled, failure is set and sbc fail- safe mode is entered. the sbc can be activated again via wake on can, wkx. ? the same behavior applies, if v cc1 falls below v rtx for longer than t vcc1,sc . note: the vcc1_sc flag is not set during power up of v cc1 . 13.8 vcc2 undervoltage and vcan undervoltage an undervoltage warning is implemented for vcc2 and vcan as follows: ? v cc2 undervoltage detection: in case v cc2 will drop below the v cc2,uv,f threshold, then the spi bit vcc2_uv is set and can be only cleared via spi. ? v can undervoltage detection: in case the voltage on v can will drop below the v can_uv threshold, then the spi bit vcan_uv is set and can be only cleared via spi. note: the vcc2_uv flag is not set during turn-on or turn-off of v cc2. ro t vcc1 t rd1 sbc normal t t ov _filt sbc restart sbc normal v cc1,ov
data sheet 87 rev. 1.1, 2014-10-23 TLE9260QXV33 supervision functions 13.9 thermal protection three independent and different thermal protection featur es are implemented in the sbc according to the system impact: ? individual thermal shutdown of specific blocks ? temperature prewarning of main microcontroller supply vcc1 ? sbc thermal shutdown due to vcc1 over temperature 13.9.1 individual thermal shutdown as a first-level protection measure t he output stages vcc2, can, and hsx are independently switched off if the respective block reaches the temperature threshold t jtsd1 . then the tsd1 bit is set. this bit can only be cleared via spi once the overtemperature is not present anymor e. independent of the sbc mode the thermal shutdown protection is only active if the respective block is on. the respective modules behave as follows: ? vcc2: is switched to off and the control bits vcc2_on are cleared. the status bit vcc2_ot is set. once the over temperature condition is not present anymor e, then vcc2 has to be configured again by spi. ? can: the transmitter is disabled an d stays in can normal mode acti ng like can receive only mode. the status bits can_fail = ?01? are set. once the over temperatur e condition is not present anymore, then the can transmitter is automatically switched on. ? hsx: if one or more hsx switches reach the tsd1 thre shold, then all hsx switches are turned off and the control bits for hsx are cleared (see registers hs_ctrl1 and hs_ctrl2 ). the status bits hsx_oc_ot are set (see register hs_oc_ot_stat ). once the over temperature condition is not present anymore, then hsx has to be configured again by spi. note: the diagnosis bits are not cleared automatically an d have to be cleared via spi once the overtemperature condition is not present anymore.
data sheet 88 rev. 1.1, 2014-10-23 TLE9260QXV33 supervision functions 13.9.2 temperature prewarning as a next level of thermal protection a temperature prewarning is implemented if the main supply vcc1 reaches the thermal prewarning temperature threshold t jpw . then the status bit tpw is set. this bit can only be cleared via spi once the overtemperature is not present anymore . independent of the sbc mode the thermal prewarning is only active if the vcc1 is on. 13.9.3 sbc thermal shutdown as a highest level of thermal protection a temperature shutdown of the sbc is impl emented if the main supply vcc1 reaches the thermal shut down temperature threshold t jtsd2 . once a tsd2 event is detected sbc fail-safe mode is entered for t tsd2 to allow the device to cool down. after this time has ex pired, the sbc will automatically change via sbc restart mode to sbc normal mode (see also chapter 5.1.6 ). when a tsd2 event is detected, then the status bit tsd2 is set. this bit can only be cleared via spi in sbc normal mode once the overtemperature is not present anymore. independent of the sbc mode the thermal shutdown is only active if vcc1 is on.
data sheet 89 rev. 1.1, 2014-10-23 TLE9260QXV33 supervision functions 13.10 electrical characteristics table 21 electrical specification v s = 5.5 v to 28 v; t j = -40 c to +150 c; sbc normal mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. parameter symbol values unit note / test condition number min. typ. max. vcc1 monitoring; vcc1 = 3.3v version undervoltage prewarning threshold voltage pw,f 3.3v option v pw,f 3.0 3.1 3.2 v vcc1 falling, spi bit is set p_15.10.36 reset threshold voltage rt1,f 3.3v option v rt1,f 2.95 3.05 3.15 v default setting; vcc1 falling p_15.10.37 reset threshold voltage rt1,r 3.3v option v rt1,r 3.0 3.1 3.2 v default setting; vcc1 rising p_15.10.38 reset threshold voltage rt2,f 3.3v option v rt2,f 2.5 2.6 2.7 v vcc1 falling p_15.10.39 reset threshold voltage rt2,r 3.3v option v rt2,r 2.55 2.65 2.75 v vcc1 rising p_15.10.40 reset threshold voltage rt3,f 3.3v option v rt3,f 2.2 2.3 2.4 v spi option; vs 4v; vcc1 falling p_15.10.41 reset threshold voltage rt3,r 3.3v option v rt3,r 2.25 2.35 2.45 v vs 4v; vcc1 rising p_15.10.42 reset threshold voltage rt4,f 3.3v option v rt4,f 2.0 2.1 2.2 v vs 4v; vcc1 falling p_15.10.43 reset threshold voltage rt4,r 3.3v option, v rt4,r 2.05 2.15 2.25 v vs 4v; vcc1 rising, p_15.10.44 reset threshold hysteresis 3.3v option v rt,hys 30 67 140 mv ? p_15.10.45 vcc1 over voltage detection threshold voltage 3.3v option v cc1,ov,r 3.4 ? 3.6 v 1)5) rising vcc1 p_15.10.70 vcc1 short to gnd filter time t vcc1,sc ?4?ms 3) p_15.10.12 reset generator; pin ro reset low output voltage v ro,l ?0.20.4v i ro = 1 ma for v cc1 1 v & v s v por,f p_15.10.14
data sheet 90 rev. 1.1, 2014-10-23 TLE9260QXV33 supervision functions reset high output voltage v ro,h 0.8 x v cc1 ? v cc1 + 0.3 v v i ro = -20 a p_15.10.15 reset pull-up resistor r ro 10 20 40 k ? v ro = 0 v p_15.10.16 reset filter time t rf 41026s 3) v cc1 < v rt1x to ro = l see also chapter 13.3 p_15.10.17 reset delay time t rd1 1.5 2 2.5 ms 2) 3) p_15.10.18 vcc2 monitoring vcc2 undervoltage threshold voltage (falling) v cc2,uv,f 4.5 ? 4.75 v vcc2 falling p_15.10.19 vcc2 undervoltage threshold voltage (rising) v cc2,uv,r 4.6 ? 4.9 v vcc2 rising p_15.10.77 v cc2 undervoltage detection hysteresis v cc2,uv, hys 20 100 250 mv ? p_15.10.20 vcan monitoring can supply under voltage detection threshold v can_uv 4.45 ? 4.85 v can normal mode, hysteresis included; p_15.10.23 watchdog generator long open window t lw ? 200 ? ms 3) p_15.10.24 internal oscillator f clksbc 0.8 1.0 1.2 mhz ? p_15.10.25 minimum waiting time during sbc fail-safe mode min. waiting time fail-safe t fs,min ? 100 ? ms 3)4) p_15.10.75 power-on reset, over / under voltage protection vs power on reset rising v por,r ? 4.5 v vs increasing p_15.10.26 vs power on reset falling v por,f ? 3 v vs decreasing p_15.10.27 vs under voltag e detection threshold 3.3v option v s,uv 3.7 ? 4.4 v supply uv threshold for vcc1 sc detection; hysteresis included p_25.10.46 vshs over voltage detection threshold v shs,ovd 20 22 v supply ov supervision for hsx; hysteresis included p_15.10.28 vshs over voltage detection hysteresis v shs,ovd,hys ? 500 ? mv 5) p_15.10.29 table 21 electrical specification (cont?d) v s = 5.5 v to 28 v; t j = -40 c to +150 c; sbc normal mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. parameter symbol values unit note / test condition number min. typ. max.
data sheet 91 rev. 1.1, 2014-10-23 TLE9260QXV33 supervision functions vshs under voltage detection threshold v shs,uvd 4.8 5.5 v supply uv supervision for hsx, and hs of gpiox; hysteresis included p_15.10.30 vshs under voltage detection hysteresis v shs,uvd,hys ? 200 ? mv 5) p_15.10.31 over temperature shutdown 5) thermal prewarning temperature t jpw 125 145 165 c p_15.10.32 thermal shutdown tsd1 t jtsd1 165 185 200 c p_15.10.33 thermal shutdown tsd2 t jtsd2 165 185 200 c p_15.10.34 thermal shutdown hysteresis t jtsd,hys ? 25 ? c p_15.10.68 deactivation time after thermal shutdown tsd2 t tsd2 ?1?s 3) p_15.10.35 1) it is ensured that the threshold v cc1,ov,r in sbc normal mode is always higher than the highest regulated v cc1 output voltage v cc1,out72 . 2) the reset delay time will start when vcc1 crosses above the selected vrtx threshold 3) not subject to production test, tolerance defined by internal oscillator tolerance. 4) this time applies for all failure entries except a de vice thermal shutdown (tsd2 has a typ. 1s waiting time t tsd2 ) 5) not subject to production test, specified by design. table 21 electrical specification (cont?d) v s = 5.5 v to 28 v; t j = -40 c to +150 c; sbc normal mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. parameter symbol values unit note / test condition number min. typ. max.
data sheet 92 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface 14 serial peripheral interface 14.1 spi block description the 16-bit wide control input word is read via the data in put sdi, which is synchroniz ed with the clock input clk provided by the microcontroller. the output word appears synchronous ly at the data output sdo (see figure 42 ). the transmission cycle begins when the chip is selected by the input csn (chip select not), low active. after the csn input returns from low to high, the word that has been read is interpreted according to the content. the sdo output switches to tristate status (high impedance ) at this point, thereby releasing the sdo bus for other use.the state of sdi is shifted into t he input register with every falling edge on clk. the state of sdo is shifted out of the output register after every rising edge on clk. the spi of the sbc is not daisy chain capable. figure 42 spi data transfer timing (note the reversed order of lsb and msb shown in this figure compared to the register description) 0 0 + 1 2 3 4 5 6 7 8 9 10 15 1 + 0 1 2 3 4 5 6 11 12 13 14 7 8 9 10 15 csn high to low: sdo is enabled. status information transferred to output shift register csn low to high: data from shift register is transferred to output functions sdi: will accept data on the falling edge of clk signal sdo: will cha nge state on the rising edge of clk signal actual status 11 12 13 14 actual data new data new status sdo sdi csn clk time time time time err err - 0 + 1 +
data sheet 93 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface 14.2 failure signalization in the spi data output when the microcontroller sends a wrong spi command to the sbc, the sbc ignores the information. wrong spi commands are either invalid sbc mode commands or commands which are prohibited by the state machine to avoid undesired device or system states (see below). in this case the diagnosis bit ? spi_fail ? is set and the spi write command is ignored (mostly no partia l interpretation). this bit can be only reset by actively clearing it via a spi command. invalid spi commands leading to spi_fail are listed below: ? illegal state transitions: going from sbc stop to sbc sl eep mode. in this case the sbc enters in addition the sbc restart mode; trying to go to sbc stop or sbc sl eep mode from sbc init mode. in this case sbc normal mode is entered; ? uneven parity in the data bit of the wd_ctrl register. in this case the watchdog trigger is ignored or the new watchdog settings are ignored respectively; ? in sbc stop mode: attempting to change any spi sett ings, e.g. changing the watchdog configuration, pwm settings and hs configuration settings during sbc stop mode, etc.; the spi command is ig nored in this case; only wd trigger, returning to normal mode, triggeri ng a sbc soft reset, and read & clear status registers commands are valid spi comma nds in sbc stop mode; ? when entering sbc stop mode and wk_stat_1 and wk_stat_2 are not cleared; spi_fail will not be set but the int pin will be triggered; ? changing from sbc stop to normal mode and changing the other bits of the m_s_ctrl register. the other modifications will be ignored; ? sbc sleep mode: attempt to go to sleep mode when all bits in the bus_ctrl_1 and wk_ctrl_2 registers are cleared. in this case the spi_fail bit is set and the sbc enters restart mode. even though the sleep mode command is not entered in this case, the rest of the command (e.g modifying vcc2 ) is executed and the values stay unchanged during sbc restart mode; note: at least one wake source must be activated in order to avoid a deadlock situation in sbc sleep mode, i.e. the sbc would not be able to wake up anymore. if the only wake source is a timer and the timer is off then the sbc will wake immedi ately from sleep mode and enter restart mode; no failure handling is done for the attempt to go to sbc stop mode when all bits in the registers bus_ctrl_1 and wk_ctrl_2 are cleared because the microcontroller can leave this mode via spi; ? attempt to enter sbc sleep mode if wk_meas is set to ?1? and only wk1_en or wk2_en are set as wake sources. also in this case the spi_fail bit is set and the sbc enters restart mode; ? setting a longer or equal on-time than th e timer period of the respective timer; ? sdi stuck at high or low, e.g. sdi received all ?0? or all ?1?; note: there is no spi fail information for unused addresses. signalization of the err flag (high ac tive) in the spi data output (see figure 42 ): the err flag presents an additional di agnosis possibility for th e spi communication. the err flag is being set for following conditions: ? in case the number of received spi clocks is not 0 or 16, ? in case ro is low and spi frames are being sent at the same time. note: in order to read the spi err flag properly, clk must be low when csn is triggere d, i.e. the err bit is not valid if the clk is high on a falling edge of csn
data sheet 94 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface the number of received spi clocks is not 0 or 16: the number of received input clocks is supervised to be 0- or 16 clock cycles and the input word is discarded in case of a mismatch (0 clock cycle to enable err signa lization). the error logic also recognizes if clk was high during csn edges. both errors - 0 bit and 16 bit clk mismatch or clk high during csn edges - are flagged in the following spi output by a ?high? at the data output (sdo pin, bit err) befo re the first rising edge of the clock is received. the complete spi command is ignored in this case. ro is low and spi frames are being sent at the same time: the err flag will be set when the ro pin is triggered (dur ing sbc restart) and spi fram es are being sent to the sbc at the same time. the behavior of the err flag will be signalized at the next spi command for below conditions: ? if the command begins when ro is high and it ends when ro is low, ? if a spi command will be sent while ro is low, ? if a spi command begins when ro is low and it ends when ro is high. and the sdo output will behave as follows: ? always when ro is low then sdo will be high, ? when a spi command begins with ro is low and ends when ro is high, then the sdo should be ignored because wrong data will be sent. note: it is possible to quickly check fo r the err flag without sending any data bits. i.e. only the csn is pulled low and sdo is observed - no spi clocks are sent in this case note: the err flag could also be set after the sbc has entered sbc fail-safe mode because the spi communication is st opped immediately.
data sheet 95 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface 14.3 spi programming for the TLE9260QXV33, 7 bits are used or the address se lection (bit6...0). bit 7 is used to decide between read only and read & clear for the status bits, and between wr ite and read only for configuration bits. for the actual configuration and status information, 8 data bits (bit15...8) are used. writing, clearing and reading is done byte wise. the sp i status bits are not cleared automatically and must be cleared by the microcontrolle r, e.g. if the tsd2 was se t due to over temp erature. the configuration bits will be partially automatically cleared by th e sbc - please refer to the individual registers description for detailed information. during sbc restart mode the spi communicati on is ignored by the sbc, i. e. it is no t interpreted. there are two types of spi registers: ? control registers: those are the registers to config ure the sbc, e.g. sbc mode, watchdog trigger, etc ? status registers: those are the registers where the status of the sbc is signalled, e.g. wake events, warnings, failures, etc. for the status registers, the requested informat ion is given in the sa me spi command in do. for the control registers, also the st atus of the respective by te is shown in the same spi command. however, if the setting is changed this is only shown with the next spi command (it is only valid after csn high) of the same register. the sbc status information from the spi status regist ers, is transmitted in a compressed way with each spi response on sdo in the so called status information field register (see also figure 43 ). the purpose of this register is to quickly signal the information to the mi crocontroller if there was a ch ange in one of the spi status registers. in this way, the microcontroller does not need to read constantly all the spi status registers but only those registers, wh ich were changed. each bit in the status information fiel d represents a spi stat us register (see table 22 ). as soon as one bit is set in one of the status register s, then the respective bit in the status information field re gister will be set. the register wk_lvl_stat is not included in the status in formation field. this is listed in table 22 . for example if bit 0 in the status information field is set to 1, one or more bits of the register 100 0001 ( sup_stat_1 ) is set to 1. then this register needs to be read in a second spi command. the bit in the status information field will be set to 0 when all bits in the regist er 100 0001 are set back to 0. table 22 status information field bit in status information field corresponding address bit status register description 0 100 0001 sup_stat_1: supply stat us -vshs fail, vccx fail, por 1 100 0010 therm_stat: thermal protection status 2 100 0011 dev_stat: device status - mode before wake, wd fail, spi fail, failure 3 100 0100 bus_stat: bus failure status: can; 4 100 0110 wk_stat_1, wk_stat_2: wake source status; status bit is set as combinat ional or of both registers 5 100 0000 sup_stat_2:vcc1_warn/ov 6 101 0100 hs_oc_ot_stat: high-side over load status 7 101 0101 hs_ol_stat: high-side open load status
data sheet 96 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface figure 43 spi operation mode 0 1 2 3 4 5 7 6 8 9 10 11 12 13 15 14 data bits di address bits x x x x x x x x r/w 0 1 2 3 4 5 7 6 8 9 10 11 12 13 15 14 data bits do status information field x x x x x x x x register content of selected address lsb msb time lsb is sent first in spi message
data sheet 97 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface 14.4 spi bit mapping the following figures show the mapping of the regist ers and the spi bits of the respective registers. the control registers ?000 0000? to ?001 1110? are read/wri te register. depending on bi t 7 the bits are only read (setting bit 7 to ?0?) or also written (setting bit 7 to ?1 ?). the new setting of the bit after write can be seen with a new read / write command. the registers ?100 0000? to ?111 1110? are status regi sters and can be read or read with clearing the bit (if possible) depending on bit 7. to clear a data byte of on e of the status r egisters bit 7 must be set to 1. the registers wk_lvl_stat , and fam_prod_stat are an exception as they show the actual voltage level at the respective wk pin (low/high), or a fixed family/ product id respectively and can t hus not be cleared. it is recommended for proper diagnosis to clear respective status bits for wake events or failure. however, in general it is possible to enable drivers withou t clearing the respec tive failure flags. when changing to a different sbc mode, certain configurations bits will be cleared automatica lly or modified: ? the sbc mode bits are updated to the actual status, e.g. when returning to normal mode ? when changing to a low-power mode (stop/sleep), the di agnosis bits of the switches and transceivers are not cleared. fox will stay activated if it was triggered before. ? when changing to sbc stop mode, the can control bits will not be modified. ? when changing to sbc sleep mode, th e can control bits will be modified if they were not off or wake capable before. ? hsx, vcc2 will stay on when goin g to sleep-/stop mode (configuration can only be done in no rmal mode). diagnosis is active (oc, ol, ot). in case of a failu re the switch is turned off and no wake-up is issued ? the configuration bits for hsx and vcc2 in stand-al one configuration are cleared in sbc restart mode. fox will stay activated if it was triggered before. depending on the respec tive configuration, can transceivers will be either off, woken or still wake capable. note: the detailed behavior of the respective spi bits and control functions is described in chapter 14.5 , chapter 14.6 .and in the respective module chapter. the bit type be mark ed as ?rwh? in case the sbc will modify respective control bits.
data sheet 98 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface figure 44 spi register mapping 0 0 0 0 1 0 1 bus_ctrl_2 rw 1 0 0 0 1 1 1 wk_stat_2 rc 4 0 0 1 0 1 1 1 gpio_ctrl rw - 15 14 13 12 11 10 8 9 7 6 5 4 3 2 0 1 7 address bits [bits 0...6] for register selection 8 data bits [bits 8...15] for configuration & status information lsb msb 0 0 0 0 0 0 1 m_s_ctrl reg. type rw 0 0 0 0 0 1 0 rw hw_ctrl 0 0 0 0 0 1 1 wd_ctrl rw 0 0 0 0 1 0 0 bus_ctrl_1 rw 0 0 0 0 1 1 0 wk_ctrl_1 rw 0 0 0 1 0 0 0 wk_pupd_ctrl rw 0 0 0 1 0 0 1 wk_flt_ctrl rw 0 0 0 1 1 0 0 timer1_ctrl rw 0 0 1 0 0 0 0 sw_sd_ctrl rw 0 0 1 0 1 0 0 hs_ctrl_1 rw 0 0 1 0 1 0 1 hs_ctrl_2 rw 0 0 1 1 0 0 0 pwm1_ctrl rw 0 0 1 1 0 0 1 pwm2_ctrl rw 1 0 0 0 0 0 1 sup_stat_1 rc 1 0 0 0 0 1 0 therm_stat rc 1 0 0 0 0 1 1 dev_stat rc 1 0 0 0 1 0 0 bus_stat_1 rc 1 0 0 0 1 1 0 wk_stat_1 rc 1 0 0 1 0 0 0 wk_lvl _stat r 1 0 1 0 1 0 0 hs_oc_ot_stat rc 1 0 1 0 1 0 1 hs_ol_stat rc 0 0 0 1 1 0 1 timer2_ctrl rw 0 0 0 0 1 1 1 wk_ctrl_2 rw 0 0 1 1 1 0 0 pwm_freq_ctrl rw 1 1 1 1 1 1 0 fam_prod_stat r 0 0 1 1 1 1 0 sys_stat_ctrl rw 1 0 0 0 0 0 0 sup_stat_2 rc status registers 0 1 2 3 4 6 7 5 status information field bit control registers
data sheet 99 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface figure 45 TLE9260QXV33 spi bit mapping 15 14 13 12 11 10 9 8 7 6...0 data bit 158 d7 d6 d5 d4 d3 d2 d1 d0 m_s_ctrl mode_1 mode_0 reserved vcc2_on_1 vcc2_on_0 vcc1_ov_rst v cc1_rt_1 vcc1_rt_0 read/write 0000001 hw_ctrl reserved soft_reset_ro fo_on reserved reserved reserved reserved cfg read/write 0000010 wd_ctrl checksum wd_stm_en_0 wd_win wd_en_wk_bus reserved wd_timer_2 wd_timer_1 wd_timer_0 read/write 0000011 bus_ctrl_1 reserved reserved reserved reserved reserved reserved can_1 can_0 read/write 0000100 bus_ctrl_2 reserved reserved i_peak_th reserved reserved reserved reserved reserved read/write 0000101 wk_ctrl_1 timer2_wk_en timer1_wk_en reserved reserved reserved wd_stm_en_1 reserved reserved read/write 0000110 wk_ctrl_2 int_global reserved wk_meas reserved reserved wk3_en wk2_en wk1_en read/write 0000111 wk_pupd_ctrl reserved reserved wk3_pupd_1 wk3_pupd_0 wk2_pupd_1 wk2_pupd_0 wk1_pupd_1 wk1_pupd_0 read/write 0001000 wk_flt_ctrl reserved reserved wk3_flt_1 wk3_flt_0 wk2_flt_1 wk2_flt_0 wk1_flt_1 wk1_flt_0 read/write 0001001 timer1_ctrl reserved timer1_on_2 timer1_on_1 timer1_on_0 reserved timer1_per_2 timer1_per_1 timer1_per_0 read/write 0001100 timer2_ctrl reserved timer2_on_2 timer2_on_1 timer2_on_0 reserved timer2_per_2 timer2_per_1 timer2_per_0 read/write 0001101 sw_sd_ctrl reserved hs_ov_sd_en hs_uv _sd_en hs_ov_uv_rec reserved reserved reserved reserved read/write 0010000 hs_ctrl_1 reserved hs2_2 hs2_1 hs2_0 reserved hs1_2 hs1_1 hs1_0 read/write 0010100 hs_ctrl_2 reserved hs4_2 hs4_1 hs4_0 reserved hs3_2 hs3_1 hs3_0 read/write 0010101 gpio_ctrl fo_dc_1 fo_dc_0 gpio2_2 gpio2_1 gpio2_0 gpi o1_2 gpio1_1 gpio1_0 read/write 0010111 pwm1_ctrl pwm1_dc_7 pwm1_dc_6 pwm1_dc_5 pwm1_dc_4 pwm1_dc_3 pwm1_dc_2 pwm1_dc_1 pwm1_dc_0 read/write 0011000 pwm2_ctrl pwm2_dc_7 pwm2_dc_6 pwm2_dc_5 pwm2_dc_4 pwm2_dc_3 pwm2_dc_2 pwm2_dc_1 pwm2_dc_0 read/write 0011001 pwm_freq_ctrl reserved reserved reserved reserved reserved pwm2_freq_0 reserved pwm1_freq_0 read/write 0011100 sys_stat_ctrl sys_stat_7 sys_stat_6 sys_stat_5 sys_stat_4 sys_st at_3 sys_stat_2 sys_stat_1 sys_stat_0 read/write 0011110 sup_stat_2 reserved vs_uv reserved reserved reserved reserved vcc1_ov vcc1_warn read/clear 1000000 sup_stat_1 por vshs_uv vshs_ov vcc2_ot vcc2_uv vcc1_sc vcc1_uv_fs vcc1_uv read/clear 1000001 therm_stat reserved reserved reserved reserved reserved tsd2 tsd1 tpw read/clear 1000010 dev_stat dev_stat_1 dev_stat_0 reserved reserved wd_fail_1 wd_fail_0 spi_fail failure read/clear 1000011 bus_stat_1 reserved reserved reserved reserved reserved can_fail_1 can_fail_0 vcan_uv read/clear 1000100 wk_stat_1 reserved reserved can_wu timer_wu reserved wk3_wu wk2_wu wk1_wu read/clear 1000110 wk_stat_2 reserved reserved gpio2_wu gpio1_wu reserved reserved reserved reserved read/clear 1000111 wk_lvl_stat sbc_dev_lvl cfgp gpio2_lvl gpio1_lvl reserved wk3_lvl wk2_lvl wk1_lvl read 1001000 hs_oc_ot_stat reserved reserved reserved reserved hs4_oc_ot hs3_oc_ot hs2_o c_ot hs1_oc_ot read/clear 1010100 hs_ol_stat reserved reserved hs4_ol hs3_ol hs2_ol hs1_ol read/clear 1010101 fam_prod_stat fam_3 fam_2 fam_1 fam_0 prod_3 prod_2 prod_1 prod_0 read 1111110 f a m i ly a n d p r o d u c t r e g i s t e r s register short name access mode address a6a0 c o n t r o l r e g i s t e r s s t a t u s r e g i s t e r s
data sheet 100 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface 14.5 spi control registers read/write operation (see also chapter 14.3 ): ? the ?por / soft reset valu e? defines the register content after por or sbc reset. ? the ?restart value? defines the register content af ter sbc restart, where ?x? means the bit is unchanged. ? one 16-bit spi command consist of two bytes: - the 7-bit address and one additional bit for the register access mode and - following the data byte the numbering of following bit definitions refers to the data byte and correspond to the bits d0...d7 and to the spi bits 8...15 (see also figure before). ? there are three different bit types: - ?r? = read: read only bits (or reserved bits) - ?rw? = read/write: read able and writable bits - ?rwh? = read/write/hardware: readable/writable bits , which can also be modified by the sbc hardware ? reserved bits are marked as ?reserved? and always read as ?0?. the respective bits shall also be programmed as ?0?. ? reading a register is done byte wise by setting the spi bit 7 to ?0? (= read only). ? writing to a register is done byte wise by setting the spi bit 7 to ?1?. ? spi control bits are in general not cleared or changed automatically. this must be done by the microcontroller via spi programming. exceptions to this behavior are stated at the respective re gister description and the respective bit type is marked with a ?h? meaning that the sbc is able to change the register content. the registers are addressed wordwise.
data sheet 101 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface 14.5.1 general control registers notes 1. it is not possible to change from stop to sleep mo de via spi command. see also the state machine chapter 2. after entering sbc restart mode , the mode bits will be automatica lly set to sbc normal mode. the vcc2_on bits will be automatically set to off after entering sbc restart mode and after ot. 3. the spi output will always show the previously written state wit h a write command (what has been programmed before) m_s_ctrl mode- and supply control (address 000 0001 b ) por / soft reset value: 0000 0000 b ; restart value: 0000 00xx b 76543210 mode_1 mode_0 reserved vcc2_on_1 vcc2_on_0 vcc1_ov_rs t vcc1_rt_1 vcc1_rt_0 r rwh rwh rwh rwh rwh rwh rw rw field bits type description mode 7:6 rwh sbc mode control 00 b , sbc normal mode 01 b , sbc sleep mode 10 b , sbc stop mode 11 b , sbc reset: soft reset is ex ecuted (configuration of ro triggering in bit soft_ reset_ro ) reserved 5r reserved, always reads as 0 vcc2_on 4:3 rwh vcc2 mode control 00 b , vcc2 off 01 b , vcc2 on in normal mode 10 b , vcc2 on in normal and stop mode 11 b , vcc2 always on (except in sbc fail-safe mode) vcc1_ov_r st 2rwh vcc1 over voltage leading to restart / fail-safe mode enable 0 b , vcc1_ ov is set in case of vcc1_o v; no sbc restart or fail- safe is entered for vcc1_ov 1 b , vcc1_ ov is set in case of vcc1_ov; depending on the device configuration sbc restart or sbc fail-safe mode is entered (see chapter 5.1.1 ); vcc1_rt 1:0 rw vcc1 reset threshold control 00 b , vrt1 selected (highest threshold) 01 b , vrt2 selected 10 b , vrt3 selected 11 b , vrt4 selected
data sheet 102 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface notes 1. clearing the fo_on bit will not disable the fox outputs fo r the case a failure occurr ed which triggered the fox outputs. in this case the fox outputs have to be disabled by clearing the failure bit. if the fo_on bit is set by the softwa re then it will be cleared by the sbc after sbc restart mode was entered and the fox outputs will be disabled. see also chapter 12 for fox activation and deactivation. hw_ctrl mode- and supply control (address 000 0010 b ) por / soft reset value: 0000 0000 b ; restart value: 0x00 000x b 76543210 reserved soft_reset _ro fo_on reserved reserved reserved reserved cfg r rrw rwhr r r rrw field bits type description reserved 7r reserved, always reads as 0 soft_ reset_ro 6rw soft reset configuration 0 b , ro will be triggered (pulle d low) during a soft reset 1 b , no ro triggering during a soft reset fo_on 5rwh failure output ac tivation (fo1..3) 0 b , fox not activated by software, fo can be activated by defined failures (see chapter 12 ) 1 b , fox activated by software (via spi) reserved 4r reserved, always reads as 0 reserved 3r reserved, always reads as 0 reserved 2r reserved, always reads as 0 reserved 1r reserved, always reads as 0 cfg 0rw configuration select (see also table 5 ) 0 b , depending on hardware configuration, sbc restart or fail- safe mode is reached after the 2. watchdog trigger failure (=default) - config 3/4 1 b , depending on hardware configuration, sbc restart or fail- safe mode is reached after the 1. watchdog trigger failure - config 1/2
data sheet 103 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface notes 1. see also chapter 13.2.4 for more information on disabling the watchdog in sbc stop mode. 2. see chapter 13.2.5 for more information on the effect of the bit wd_en_wk_bus. 3. see chapter 13.2.3 for calculation of checksum. wd_ctrl watchdog control (address 000 0011 b ) por / soft reset value: 0001 0100 b ; restart value: x0xx 0100 b 76543210 checksum wd_stm_ en_0 wd_win wd_en_ wk_bus reserved wd_timer_2 wd_timer_1 wd_timer_0 r rw rwh rw rw r rwh rwh rwh field bits type description checksum 7rw watchdog setting check sum bit the sum of bits 7:0 needs to have even parity (see chapter 13.2.3 ) 0 b , counts as 0 for checksum calculation 1 b , counts as 1 for checksum calculation wd_stm_ en_0 6rwh watchdog deactivation during stop mode, bit 0 ( chapter 13.2.4 ) 0 b , watchdog is active in stop mode 1 b , watchdog is deactivated in stop mode wd_win 5rw watchdog type selection 0 b , watchdog works as a time-out watchdog 1 b , watchdog works as a window watchdog wd_en_ wk_bus 4rwh watchdog enable after bus (can) wake in sbc stop mode 0 b , watchdog will not start after a can wake 1 b , watchdog starts with a long open window after can wake reserved 3r reserved, always reads as 0 wd_timer 2:0 rwh watchdog timer period 000 b , 10ms 001 b , 20ms 010 b , 50ms 011 b , 100ms 100 b , 200ms 101 b , 500ms 110 b , 1000ms 111 b , reserved
data sheet 104 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface notes 1. the reset values for the can transce ivers are marked with ?y? because they will vary depending on the cause of change - see below. 2. see figure 19 for detailed state changes of can transceiver for different sbc modes. 3. failure handling mechanism: when th e device enters fail-safe mode due to a failure (tsd2, wd-failure,...), then the wake registers bus_ctrl_1 and wk_ctrl_2 are reset to follo wing values (=wake sources) ?xxx0 0001? and ?x0x0 0111? in order to ensure that the device can be woken again. bus_ctrl_1 bus control (address 000 0100 b ) por / soft reset value: 0000 0000 b ; restart value: 0000 00yy b 76543210 reserved reserved reserved reserved reserved reserved can_1 can_0 r rrrrrrrwhrwh field bits type description reserved 7:3 r reserved, always reads as 0 reserved 2r reserved, always reads as 0 can 1:0 rwh hs-can module modes 00 b , can off 01 b , can is wake capable 10 b , can receive only mode 11 b , can normal mode
data sheet 105 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface notes 1. the bit i_peak_th can be modified in sbc init and normal mode . in sbc stop mode this bit is read only but spi_fail will not be set when trying to modify the bit in sbc stop mode and no in t is triggered in case int_ global is set. 2. see figure 19 for detailed state changes of can transceiver for different sbc modes 3. failure handling mechanism: when th e device enters fail-safe mode due to a failure (tsd2, wd-failure,...), then the wake registers bus_ctrl_1 , and wk_ctrl_2 are reset to following values (=wake sources) ?xxx0 1001?, and ?x0x0 0111? in order to ensure that the device can be woken again. bus_ctrl_2 bus control (address 000 0101 b ) por / soft reset value: 0000 0000 b ; restart value: 00x0 0000 b 76543210 reserved reserved i_peak_th reserved reserved reserved reserved reserved r rrrwrrrrr field bits type description reserved 7:6 r reserved, always reads as 0 i_peak_th 5rw vcc1 active peak threshold selection 0 b , low vcc1 active peak threshold selected (icc1,peak_1) 1 b , higher vcc1 active peak threshold selected (icc1,peak_2) reserved 4:0 r reserved, always reads as 0
data sheet 106 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface wk_ctrl_1 internal wake input control (address 000 0110 b ) por / soft reset value: 0000 0000 b ; restart value: xx00 0000 b 76543210 timer2_wk_ en timer1_wk_ en reserved reserved reserved wd_stm_ en_1 reserved reserved r rw rw r r r rwh r r field bits type description timer2_wk _en 7rw timer2 wake source control (for cyclic wake) 0 b , timer2 wake disabled 1 b , timer2 is enabled as a wake source timer1_wk _en 6rw timer1 wake source control (for cyclic wake) 0 b , timer1 wake disabled 1 b , timer1 is enabled as a wake source reserved 5:3 r reserved, always reads as 0 wd_stm_ en_1 2rwh watchdog deactivation during stop mode, bit 1 ( chapter 13.2.4 ) 0 b , watchdog is active in stop mode 1 b , watchdog is deactivated in stop mode reserved 1:0 r reserved, always reads as 0
data sheet 107 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface notes 1. wk_meas is by default conf igured for standard wk functionality (wk1 and wk2). the bits wk1_en and wk2_en are ignored in case wk_meas is activated. if the bit is set to ?1 ? then the measurem ent function is enabled during normal mode & the bits wk1_en and wk 2_en are ignored. the bits wk1/?_lvl bits need to be ignored as well. 2. the wake sources can are selected in the register bus_ctrl_1 by setting the respec tive bits to ?wake capable? 3. failure handling mechanism: when th e device enters fail-safe mode due to a failure (tsd2, wd-failure,...), then the wake registers bus_ctrl_1 and wk_ctrl_2 are reset to follo wing values (=wake sources) ?xxx0 0001? and ?x0x0 0111? in order to ensure that the device can be woken again. wk_ctrl_2 external wake source control (address 000 0111 b ) por / soft reset value: 0000 0111 b ; restart value: x0x0 0xxx b 76543210 int_global reserved wk_meas reserved reserved wk3_en wk2_en wk1_en w r rw r rw r r rw rw rw field bits type description int_ global 7rw global interrupt configuration (see also chapter 11.1 ) 0 b , only wake sources trigger int (default) 1 b , all status information register bits will trigger int (including all wake sources) reserved 6r reserved, always reads as 0 wk_meas 5rw wk / measurement selection (see also chapter 10.2.2 ) 0 b , wk functionality enabled for wk1 and wk2 1 b , measurement functionality enabled; wk1 & wk2 are disabled as wake sources, i.e. bits wk1/2_en bits are ignored reserved 4:3 r reserved, always reads as 0 wk3_en 2rw wk3 wake source control 0 b , wk3 wake disabled 1 b , wk3 is enabled as a wake source wk2_en 1rw wk2 wake source control 0 b , wk2 wake disabled 1 b , wk2 is enabled as a wake source wk1_en 0rw wk1 wake source control 0 b , wk1 wake disabled 1 b , wk1 is enabled as a wake source
data sheet 108 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface wk_pupd_ctrl wake input level control (address 000 1000 b ) por / soft reset value: 0000 0000 b ; restart value: 00xx xxxx b 76543210 reserved reserved wk3_pupd_1 wk3_pupd_0 wk2_pupd_1 wk2_pupd_0 wk1_pupd_1 wk1_pupd_0 r r r rw rw rw rw rw rw field bits type description reserved 7:6 r reserved, always reads as 0 wk3_pupd 5:4 rw wk3 pull-up / pull-do wn configuration 00 b , no pull-up / pull-down selected 01 b , pull-down resistor selected 10 b , pull-up resistor selected 11 b , automatic switching to pull-up or pull-down wk2_pupd 3:2 rw wk2 pull-up / pull-do wn configuration 00 b , no pull-up / pull-down selected 01 b , pull-down resistor selected 10 b , pull-up resistor selected 11 b , automatic switching to pull-up or pull-down wk1_pupd 1:0 rw wk1 pull-up / pull-do wn configuration 00 b , no pull-up / pull-down selected 01 b , pull-down resistor selected 10 b , pull-up resistor selected 11 b , automatic switching to pull-up or pull-down
data sheet 109 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface note: when selecting a filter time configuration, the user mu st make sure to also assign the respective timer to at least one hs switch during cyclic sense operation wk_flt_ctrl wake input filter time control (address 000 1001 b ) por / soft reset value: 0000 0000 b ; restart value: 00xx xxxx b 76543210 reserved reserved wk3_flt_1 wk3_flt_0 wk2_flt_1 wk2_flt_0 wk1_flt_1 wk1_flt_0 r r r rw rw rw rw rw rw field bits type description reserved 7:6 r reserved, always reads as 0 wk3_flt 5:4 rw wk3 filter time configuration 00 b , configuration a: filt er with 16s filter time (static sensing) 01 b , configuration b: filt er with 64s filter time (static sensing) 10 b , configuration c: filtering at the end of the on-time; a filter time of 16s (cyclic sensing) is selected, timer1 11 b , configuration d: filtering at the end of the on-time; a filter time of 16s (cyclic sensing) is selected, timer2 wk2_flt 3:2 rw wk2 filter time configuration 00 b , configuration a: filt er with 16s filter time (static sensing) 01 b , configuration b: filt er with 64s filter time (static sensing) 10 b , configuration c: filtering at the end of the on-time; a filter time of 16s (cyclic sensing) is selected, timer1 11 b , configuration d: filtering at the end of the on-time; a filter time of 16s (cyclic sensing) is selected, timer2 wk1_flt 1:0 rw wk1 filter time configuration 00 b , configuration a: filt er with 16s filter time (static sensing) 01 b , configuration b: filt er with 64s filter time (static sensing) 10 b , configuration c: filtering at the end of the on-time; a filter time of 16s (cyclic sensing) is selected, timer1 11 b , configuration d: filtering at the end of the on-time; a filter time of 16s (cyclic sensing) is selected, timer2
data sheet 110 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface notes 1. a timer must be first assigned and is then automati cally activated as soon as the on-time is configured. 2. if cyclic sense is selected and the hs switches ar e cleared during sbc restart mode, then also the timer settings (period and on-time) are clear ed to avoid incorrect switch detection. 3. in case the timer are set as wake sources and cyclic se nse is running, then both cyclic sense and cyclic wake will be active at the same time. timer1_ctrl timer1 control and selection (address 000 1100 b ) por / soft reset value: 0000 0000 b ; restart value: 0000 0000 b 76543210 reserved timer1_ on_2 timer1_ on_1 timer1_ on_0 reserved timer1_ per_2 timer1_ per_1 timer1_ per_0 r r rwh rwh rwh r rwh rwh rwh field bits type description reserved 7r reserved, always reads as 0 timer1_ on 6:4 rwh timer1 on-time configuration 000 b , off / low (timer not running, hsx output is low) 001 b , 0.1ms on-time 010 b , 0.3ms on-time 011 b , 1.0ms on-time 100 b , 10ms on-time 101 b , 20ms on-time 110 b , off / high (timer not running, hsx output is high) 111 b , reserved reserved 3r reserved, always reads as 0 timer1_ per 2:0 rwh timer1 period configuration 000 b , 10ms 001 b , 20ms 010 b , 50ms 011 b , 100ms 100 b , 200ms 101 b , 1s 110 b , 2s 111 b , reserved
data sheet 111 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface notes 1. a timer must be first assigned and is then automati cally activated as soon as the on-time is configured. 2. if cyclic sense is selected and the hs switches ar e cleared during sbc restart mode, then also the timer settings (period and on-time) are clear ed to avoid incorrect switch detection. timer2_ctrl timer2 control and selection (address 000 1101 b ) por / soft reset value: 0000 0000 b ; restart value: 0000 0000 b 76543210 reserved timer2_ on_2 timer2_ on_1 timer2_ on_0 reserved timer2_ per_2 timer2_ per_1 timer2_ per_0 r r rwh rwh rwh r rwh rwh rwh field bits type description reserved 7r reserved, always reads as 0 timer2_ on 6:4 rwh timer2 on-time configuration 000 b , off / low (timer not running, hsx output is low) 001 b , 0.1ms on-time 010 b , 0.3ms on-time 011 b , 1.0ms on-time 100 b , 10ms on-time 101 b , 20ms on-time 110 b , off / high (timer not running, hsx output is high) 111 b , reserved reserved 3r reserved, always reads as 0 timer2_ per 2:0 rwh timer2 period configuration 000 b , 10ms 001 b , 20ms 010 b , 50ms 011 b , 100ms 100 b , 200ms 101 b , 1s 110 b , 2s 111 b , reserved
data sheet 112 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface sw_sd_ctrl switch shutdown control (address 001 0000 b ) por / soft reset value: 0000 0000 b ; restart value: 0xxx 0000 b 76543210 reserved hs_ov_sd_e n hs_uv_sd_e n hs_ov_uv_r ec reserved reserved reserved reserved r rrwrwrwr r r r field bits type description reserved 7r reserved, always reads as 0 hs_ov_sd_ en 6rw shutdown disabling of hs1...4 in case of vshs ov 0 b , shutdown enabled in case of vshs ov 1 b , shutdown disabled in case of vshs ov hs_uv_sd_ en 5rw shutdown disabling of hs1...4 in case of vshs uv 0 b , shutdown enabled in case of vshs uv 1 b , shutdown disabled in case of vshs uv hs_ov_uv_ rec 4rw switch recovery after remova l of vshs ov/uv for hs1...4 0 b , switch recovery is disabled 1 b , previous state before vshs ov/uv is enabled after ov/uv condition is removed reserved 3:0 r reserved, always reads as 0
data sheet 113 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface note: the bits for the switches are also reset in case of overcurrent and overtemperature. hs_ctrl1 high-side switch control 1 (address 001 0100 b ) por / soft reset value: 0000 0000 b ; restart value: 0000 0000 b 76543210 reserved hs2_2 hs2_1 hs2_0 reserved hs1_2 hs1_1 hs1_0 r rw rwh rwh rwh r rwh rwh rwh field bits type description reserved 7r reserved, always reads as 0 hs2 6:4 rwh hs2 configuration 000 b , off 001 b , on 010 b , controlled by timer1 011 b , controlled by timer2 100 b , controlled by pwm1 101 b , controlled by pwm2 110 b , reserved 111 b , reserved reserved 3r reserved, always reads as 0 hs1 2:0 rwh hs1 configuration 000 b , off 001 b , on 010 b , controlled by timer1 011 b , controlled by timer2 100 b , controlled by pwm1 101 b , controlled by pwm2 110 b , reserved 111 b , reserved
data sheet 114 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface note: the bits for the switches are also reset in case of overcurrent and overtemperature. hs_ctrl2 high-side switch control 2 (address 001 0101 b ) por / soft reset value: 0000 0000 b ; restart value: 0000 0000 b 76543210 reserved hs4_2 hs4_1 hs4_0 reserved hs3_2 hs3_1 hs3_0 r r rwh rwh rwh r rwh rwh rwh field bits type description reserved 7r reserved, always reads as 0 hs4 6:4 rwh hs4 configuration 000 b , off 001 b , on 010 b , controlled by timer1 011 b , controlled by timer2 100 b , controlled by pwm1 101 b , controlled by pwm2 110 b , reserved 111 b , reserved reserved 3r reserved, always reads as 0 hs3 2:0 rwh hs3 configuration 000 b , off 001 b , on 010 b , controlled by timer1 011 b , controlled by timer2 100 b , controlled by pwm1 101 b , controlled by pwm2 110 b , reserved 111 b , reserved
data sheet 115 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface note: when selecting a filter time configuration, the user mu st make sure to also assign the respective timer to at least one hs switch during cyclic sense operation gpio_ctrl gpio configuration control (address 001 0111 b ) por / soft reset value: 0000 0000 b ; restart value: xxxx xxxx b 76543210 fo_dc_1 fo_dc_0 gpio2_2 gpio2_1 gp io2_0 gpio1_2 gpio1_1 gpio1_0 r rw rw rw rw rw rw rw rw field bits type description fo_dc 7:6 rw duty cycle configuration of fo3 (if selected) 00 b , 20% 01 b , 10% 10 b , 5% 11 b , 2.5% gpio2 5:3 rw gpio2 configuration 000 b , fo3 selected 001 b , fo3 selected 010 b , fo3 selected 011 b , fo3 selected 100 b , off 101 b , wake input enabled (16s static filter) 110 b , low-side switch on 111 b , high-side switch on gpio1 2:0 rw gpio1 configuration 000 b , fo2 selected 001 b , fo2 selected 010 b , fo2 selected 011 b , fo2 selected 100 b , off 101 b , wake input enabled (16s static filter) 110 b , low-side switch on 111 b , high-side switch on
data sheet 116 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface note: the min. on-time during pwm is limited by the actual ton and toff time of the respective hs switch, e.g. the pwm setting ?000 0001? could not be realized. note: the min. on-time during pwm is limited by the actual ton and toff time of the respective hs switch, e.g. the pwm setting ?000 0001? could not be realized. pwm1_ctrl pwm1 configuration control (address 001 1000 b ) por / soft reset value: 0000 0000 b ; restart value: xxxx xxxx b 76543210 pwm1_dc_7 pwm1_dc_6 pwm1_dc_5 pwm1_dc_4 pwm1_dc_3 pwm1_dc_2 pwm1_dc_1 pwm1_dc_0 r rw rw rw rw rw rw rw rw field bits type description pwm1_dc 7:0 rw pwm1 duty cycle (bit0=lsb; bit7=msb) 0000 0000 b , 100% off xxxx xxxx b , on with dc fraction of 255 1111 1111 b , 100% on pwm2_ctrl pwm2 configuration control (address 001 1001 b ) por / soft reset value: 0000 0000 b ; restart value: xxxx xxxx b 76543210 pwm2_dc_7 pwm2_dc_6 pwm2_dc_5 pwm2_dc_4 pwm2_dc_3 pwm2_dc_2 pwm2_dc_1 pwm2_dc_0 r rw rw rw rw rw rw rw rw field bits type description pwm2_dc 7:0 rw pwm2 duty cycle (bit0=lsb; bit7=msb) 0000 0000 b , 100% off xxxx xxxx b , on with dc fraction of 255 1111 1111 b , 100% on
data sheet 117 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface note: the min. on-time during pwm is limited by the actual ton and toff time of the respective hs switch, e.g. the pwm setting ?000 0001? could not be realized. notes 1. the sys_status_ctrl register is an exception for the default values, i.e. it will ke ep its configured value also after a soft reset. 2. this byte is intended for storing system configurations of the ecu by the microcontroller and is only accessible in sbc normal mode. the byte is not accessible by t he sbc and is also not cleared after fail-safe or sbc restart mode. it allows the microcon troller to quickly store system co nfiguration without loosing the data. pwm_freq_ctrl pwm frequency configuration control (address 001 1100 b ) por / soft reset value: 0000 0000 b ; restart value: 0000 0x0x b 76543210 reserved reserved reserved reserved reserved pwm2_freq reserved pwm1_freq r rrrrrrwrrw field bits type description reserved 7:3 r reserved, always reads as 0 pwm2_ freq 2rw pwm2 frequency selection 0 b , 200hz configuration 1 b , 400hz configuration reserved 1r reserved, always reads as 0 pwm1_ freq 0rw pwm1 frequency selection 0 b , 200hz configuration 1 b , 400hz configuration sys_status_ctrl system status control (address 001 1110 b ) por value: 0000 0000 b ; restart value/soft reset value: xxxx xxxx b 76543210 sys_stat_7 sys_stat_6 sys_stat_5 sys_stat_4 sys_stat_3 sys_stat_2 sys_stat_1 sys_stat_0 r rw rw rw rw rw rw rw rw field bits type description sys_stat 7:0 rw system status control byte (bit0=lsb; bit7=msb) dedicated byte for system co nfiguration, access only by microcontroller. cleared after power up and soft reset
data sheet 118 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface 14.6 spi status information registers read/clear operation (see also chapter 14.3 ): ? one 16-bit spi command consist of two bytes: - the 7-bit address and one additional bit for the register access mode and - following the data byte the numbering of following bit definitions refers to the data byte and correspond to the bits d0...d7 and to the spi bits 8...15 (see also figure). ? there are two different bit types: - ?r? = read: read only bits (or reserved bits) - ?rc? = read/clear: readable and clearable bits ? reading a register is done byte wise by setting the spi bit 7 to ?0? (= read only) ? clearing a register is done byte wise by setting the spi bit 7 to ?1? ? spi status registers are in general not cleare d or changed automatically (an exception are the wd_fail bits). this must be done by the microcontroller via spi command the registers are addressed wordwise.
data sheet 119 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface 14.6.1 general status registers notes 1. the vcc1 undervoltage prewarning threshold v pw,f / v pw,r is a fixed threshold and independent of the vcc1 undervoltage reset thresholds. sup_stat_2 supply voltage fail status (address 100 0000 b ) por / soft reset value: 0000 0000 b ; restart value: 0x00 00xx b 76543210 reserved vs_uv reserved reserved reserved reserved vcc1_ov vcc1_warn r rrcr r r rrcrc field bits type description reserved 7r reserved, always reads as 0 vs_uv 6rc vs under-voltage detection ( v s,uv ) 0 b , no vs under voltage detected 1 b , vs under voltage detected reserved 5r reserved, always reads as 0 reserved 4:2 r reserved, always reads as 0 vcc1_ ov 1rc vcc1 over voltage detection ( v cc1,ov,r ) 0 b , no vcc1 over voltage warning 1 b , vcc1 over voltage detected vcc1_ warn 0rc vcc1 undervoltage prewarning ( v pw,f ) 0 b , no vcc1 undervoltage prewarning 1 b , vcc1 undervoltage prewarning detected
data sheet 120 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface notes 1. the msb of the por/soft reset value is marked as ?y?: the default value of the por bit is set after power-on reset (por value = 1000 0000). however it will be clear ed after a sbc soft reset command (soft reset value = 0000 0000). 2. during sleep mode, the bits vcc1_sc,vcc1_o v and vcc1_uv will not be set when vcc1 is off 3. the vcc1_uv bit is never updated in sbc restart mode, in sbc init mode it is only updated after ro was released for the first time, it is a lways updated in sbc normal and stop mode, and it is always updated in any sbc modes in a vcc1_sc condition (after vcc1_uv = 1 for >4ms). sup_stat_1 supply voltage fail status (address 100 0001 b ) por / soft reset value: y000 0000 b ; restart value: xxxx xx0x b 76543210 por vshs_uv vshs_ov vcc2_ot vcc 2_uv vcc1_sc vcc1_uv_fs vcc1_uv r rc rc rc rc rc rc rc rc field bits type description por 7rc power-on reset detection 0 b , no por 1 b , por occurred vshs_uv 6rc vshs under-voltage detection ( v shs,uvd ) 0 b , no vshs-uv 1 b , vshs-uv detected vshs_ov 5rc vshs over-voltage detection ( v shs,ovd ) 0 b , no vshs-ov 1 b , vshs-ov detected vcc2_ot 4rc vcc2 over temperature detection 0 b , no over temperature 1 b , vcc2 over temperature detected vcc2_uv 3rc vcc2 under voltage detection ( v cc2,uv,f ) 0 b , no vcc2 under voltage 1 b , vcc2 under voltage detected vcc1_sc 2rc vcc1 short to gnd detection (4ms after switch on) 0 b , no short 1 b , vcc1 short to gnd detected vcc1_uv _fs 1rc vcc1 uv-detection (due to vrtx reset) 0 b , no fail-safe mode entry due to 4th consecutive vcc1_uv 1 b , fail-safe mode entry due to 4th consecutive vcc1_uv vcc1_uv 0rc vcc1 uv-detection (due to vrtx reset) 0 b , no vcc1_uv detection 1 b , vcc1 uv-fail detected
data sheet 121 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface note: tsd1 and tsd2 are not reset automatically, even if the temperature pre warning or tsd1 ot condition is not present anymore. also tsd2 is not reset. therm_stat thermal protection status (address 100 0010 b ) por / soft reset value: 0000 0000 b ; restart value: 0000 0xxx b 76543210 reserved reserved reserved reserved reserved tsd2 tsd1 tpw r rrrrrrcrcrc field bits type description reserved 7:3 r reserved, always reads as 0 tsd2 2rc tsd2 thermal shut-down detection 0 b , no tsd2 event 1 b , tsd2 ot detected - lead ing to sbc fail-safe mode tsd1 1rc tsd1 thermal shut-down detection 0 b , no tsd1 fail 1 b , tsd1 ot detected tpw 0rc thermal pre warning 0 b , no thermal pre warning 1 b , thermal pre warning detected
data sheet 122 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface notes 1. the bits dev_stat show the status of the device before it went through restart. either the device came from regular sleep mode (?10?) or a failure (?01? - sbc restar t or sbc fail-safe mode: wd fail, tsd2 fail, vcc_uv fail or vcc1_ov if bit vcc1_ov_rst is set) occurred. failure is also an illegal command fr om sbc stop to sbc sleep mode or going to sbc sleep mode without ac tivation of any wake source. coming from sbc sleep mode (?10?) will also be shown if there was a trial to enter sbc sleep mode withou t having cleared all wake flags before. 2. the wd_fail bits are configured as a counter and are the on ly status bits, which ar e cleared automatically by the sbc. they are cleared after a successful watchdo g trigger and when the watchdog is stopped (also in sbc sleep and fail-safe mode unless it was reached due to a watchdog failure). see also chapter 12.1 . 3. the spi_fail bit is cleared only by spi command 4. in case of config 2/4 the wd_fail counter is frozen in case of wd trigger failure until a successful wd trigger. 5. if cfg = ?0? then a 1st watchdog fa ilure will not trigger the fo outputs or the fail ure bit but only force the sbc into sbc restart mode. dev_stat device information status (address 100 0011 b ) por / soft reset value: 0000 0000 b ; restart value: xx00 xxxx b 76543210 dev_stat_1 dev_stat_0 reserved reserved wd_fail_1 wd_fail_0 spi_fail failure r rc rc r r rh rh rc rc field bits type description dev_stat 7:6 rc device status before restart mode 00 b , cleared (register must be actively cleared) 01 b , restart due to failu re (wd fail, tsd2, vcc1_uv); also after a wake from fail-safe mode 10 b , sleep mode 11 b , reserved reserved 5:4 r reserved, always reads as 0 wd_fail 3:2 rh number of wd-failure events (1/2 wd failures depending on cfg ) 00 b , no wd fail 01 b , 1x wd fail, fox activa tion - config 2 selected 10 b , 2x wd fail, fox activation - config 1 / 3 / 4 selected 11 b , reserved (never reached) spi_fail 1rc spi fail information 0 b , no spi fail 1 b , invalid spi command detected failure 0rc activation of fail output fo 0 b , no failure 1 b , failure occurred
data sheet 123 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface notes 1. the vcan_uv comparator is enabled if the mode bit ca n_1 = ?1?, i.e. in can no rmal or can receive only mode. bus_stat_1 bus communication status (address 100 0100 b ) por / soft reset value: 0000 0000 b ; restart value: 0000 0xxx b 76543210 reserved reserved reserved reserved reserved can_fail_1 can_fail_0 vcan_uv r rrrrrrcrcrc field bits type description reserved 7r reserved, always reads as 0 reserved 6:5 r reserved, always reads as 0 reserved 4:3 r reserved, always reads as 0 can_fail 2:1 rc can failure status 00 b , no error 01 b , can tsd 10 b , can_txd_dom: txd dominant time out for more than 4ms 11 b , can_bus_dom: bus dominant time out for more than 4ms vcan_uv 0rc under voltage can bus supply 0 b , normal operation 1 b , can supply under voltage detected. transmitter disabled
data sheet 124 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface note: the respective wake source bit will also be set when the dev ice is woken from sbc fail-safe mode wk_stat_1 wake-up source and information status (address 100 0110 b ) por / soft reset value: 0000 0000 b ; restart value: 00xx 0xxx b 76543210 reserved reserved can_wu timer_wu reserved wk3_wu wk2_wu wk1_wu r rrrcrcrrcrcrc field bits type description reserved 7r reserved, always reads as 0 reserved 6r reserved, always reads as 0 can_wu 5rc wake up via can bus 0 b , no wake up 1 b , wake up timer_wu 4rc wake up via timerx 0 b , no wake up 1 b , wake up reserved 3r reserved, always reads as 0 wk3_wu 2rc wake up via wk3 0 b , no wake up 1 b , wake up wk2_wu 1rc wake up via wk2 0 b , no wake up 1 b , wake up wk1_wu 0rc wake up via wk1 0 b , no wake up 1 b , wake up
data sheet 125 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface wk_stat_2 wake-up source and information status (address 100 0111 b ) por / soft reset value: 0000 0000 b ; restart value: 00xx 0000 b 76543210 reserved reserved gpio2_wu gpio1_wu reserved reserved reserved reserved r rrrcrcrrrr field bits type description reserved 7:6 r reserved, always reads as 0 gpio2_wu 5rc wake up via gpio2 0 b , no wake up 1 b , wake up gpio1_wu 4rc wake up via gpio1 0 b , no wake up 1 b , wake up reserved 3:0 r reserved, always reads as 0
data sheet 126 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface note: gpiox_lvl is updated in sbc normal and stop mode if configured as wake input, low-side switch or high- side switch. in cyclic sense or wake mode, the registers contain th e sampled level, i.e. the registers are updated after every sampling. the gpios are not capable of cyclic sensing. if selected as gpio then the respective level is sh own even if configured as low-side or high-side. wk_lvl_stat wk input level (address 100 1000 b ) por / soft reset value: xx00 0xxx b ; restart value: xxxx 0xxx b 76543210 sbc_dev _lvl cfgp gpio2_lvl gpio1_lvl reserved wk3_lvl wk2_lvl wk1_lvl r rrrrrrrr field bits type description sbc_dev _lvl 7r status of sbc operating mode at fo3/test pin 0 b , user mode activated 1 b , sbc software development mode activated cfgp 6r device configuration status 0 b , no external pull-up resistor connected on int (config 2/4) 1 b , external pull-up resistor connected on int (config 1/3) gpio2_lvl 5r status of gpio2 (if selected as gpio) 0 b , low level (=0) 1 b , high level (=1) gpio1_lvl 4r status of gpio1 (if selected as gpio) 0 b , low level (=0) 1 b , high level (=1) reserved 3r reserved, always reads as 0 wk3_lvl 2r status of wk3 0 b , low level (=0) 1 b , high level (=1) wk2_lvl 1r status of wk2 0 b , low level (=0) 1 b , high level (=1) wk1_lvl 0r status of wk1 0 b , low level (=0) 1 b , high level (=1)
data sheet 127 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface note: the oc/ot bit might be set for v por,f < vs < 5.5v (see also chapter 4.2 ) hs_oc_ot_stat high-side switch overload status (address 101 0100 b ) por / soft reset value: 0000 0000 b ; restart value: 0000 xxxx b 76543210 reserved reserved reserved reserved hs4_oc_ot hs3_oc_ot hs2_oc_ot hs1_oc_ot r rrrrrcrcrcrc field bits type description reserved 7:4 r reserved, always reads as 0 hs4_oc_ot 3rc over-current & over-temperature detection hs4 0 b , no oc or ot 1 b , oc or ot detected hs3_oc_ot 2rc over-current & over-temperature detection hs3 0 b , no oc or ot 1 b , oc or ot detected hs2_oc_ot 1rc over-current & over-temperature detection hs2 0 b , no oc or ot 1 b , oc or ot detected hs1_oc_ot 0rc over-current & over-temperature detection hs1 0 b , no oc or ot 1 b , oc or ot detected
data sheet 128 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface hs_ol_stat high-side switch open-load status (address 101 0101 b ) por / soft reset value: 0000 0000 b ; restart value: 0000 xxxx b 76543210 reserved reserved reserved reserved hs4_ol hs3_ol hs2_ol hs1_ol r rrrrrcrcrcrc field bits type description reserved 7:4 r reserved, always reads as 0 hs4_ol 3rc open-load detection hs4 0 b , no ol 1 b , ol detected hs3_ol 2rc open-load detection hs3 0 b , no ol 1 b , ol detected hs2_ol 1rc open-load detection hs2 0 b , no ol 1 b , ol detected hs1_ol 0rc open-load detection hs1 0 b , no ol 1 b , ol detected
data sheet 129 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface 14.6.2 family and produc t information register notes 1. the actual default register value after por, soft reset or restart of prod will depend on the respective product. therefore the value ?y? is specified. 2. swk = selective wake feature in can partial networking standard fam_prod_stat family and product identification register (address 111 1110 b ) por / soft reset value: 0011 yyyy b ; restart value: 0011 yyyy b 76543210 fam_3 fam_2 fam_1 fam_0 pr od_3 prod_2 prod_1 prod_0 r rrrrrrrr field bits type description fam 7:4 r sbc family identifier (bit4=lsb; bit7=msb) 0 0 01 b , driver sbc family 0 0 10 b , dc/dc-sbc family 0 0 11 b , mid-range sbc family x x x x b , reserved for future products prod 3:0 r sbc product identifier (bit0=lsb; bit3=msb) 0 0 0 1 b , TLE9260QXV33 (vcc1 = 3.3v, no lin, no vcc3, no swk) 0 1 0 1 b , tle9261qxv33 (vcc1 = 3.3v, no lin, vcc3, no swk) 1 0 0 1 b , tle9262qxv33 (vcc1 = 3.3v, 1 lin, vcc3, no swk) 1 1 0 1 b , tle9263qxv33 (vcc1 = 3.3v, 2 lin, vcc3, no swk)
data sheet 130 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface 14.7 electrical characteristics table 23 electrical characteristics v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. spi frequency maximum spi frequency f spi,max ??4.0mhz 1) p_16.7.1 spi interface; logic inputs sdi, clk and csn h-input voltage threshold v ih ? ? 0.7* v cc1 v ? p_16.7.2 l-input voltage threshold v il 0.3* v cc1 ? ? v ? p_16.7.3 hysteresis of input voltage v ihy ?0.12* v cc1 ?v 1) p_16.7.4 pull-up resistance at pin csn r icsn 20 40 80 k ? v csn = 0.7 x v cc1 p_16.7.5 pull-down resistance at pin sdi and clk r iclk/sdi 20 40 80 k ? v sdi/clk = 0.2 x v cc1 p_16.7.6 input capacitance at pin csn, sdi or clk c i ?10?pf 1) p_16.7.7 logic output sdo h-output voltage level v sdoh v cc1 - 0.4 v cc1 - 0.2 ?v i doh = -1.6 ma p_16.7.8 l-output voltage level v sdol ?0.20.4v i dol = 1.6 ma p_16.7.9 tristate leakage current i sdolk -10 ? 10 a v csn = v cc1 ; 0 v < v do < v cc1 p_16.7.10 tristate input capacitance c sdo ?1015pf 1) p_16.7.11 data input timing 1) clock period t pclk 250 ? ? ns ? p_16.7.12 clock high time t clkh 125 ? ? ns ? p_16.7.13 clock low time t clkl 125 ? ? ns ? p_16.7.14 clock low before csn low t bef 125 ? ? ns ? p_16.7.15 csn setup time t lead 250 ? ? ns ? p_16.7.16 clk setup time t lag 250 ? ? ns ? p_16.7.17 clock low after csn high t beh 125 ? ? ns ? p_16.7.18 sdi set-up time t disu 100 ? ? ns ? p_16.7.19 sdi hold time t diho 50 ? ? ns ? p_16.7.20 input signal rise time at pin sdi, clk and csn t rin ? ? 50 ns ? p_16.7.21 input signal fall time at pin sdi, clk and csn t fin ? ? 50 ns ? p_16.7.22 delay time for mode changes 2) t del,mode ??6sincludes internal oscillator tolerance p_16.7.23
data sheet 131 rev. 1.1, 2014-10-23 TLE9260QXV33 serial peripheral interface figure 46 spi timing diagram note: numbers in drawing correlate to the last 2 digits of the number field in the elec trical characteristics table. csn high time t csn(high) 3??s? p_16.7.24 data output timing 1) sdo rise time t rsdo ?3080ns c l = 100 pf p_16.7.25 sdo fall time t fsdo ?3080ns c l = 100 pf p_16.7.26 sdo enable time t ensdo ? ? 50 ns low impedance p_16.7.27 sdo disable time t dissdo ? ? 50 ns high impedance p_16.7.28 sdo valid time t vasdo ??50ns c l = 100 pf p_16.7.29 1) not subject to production test; specified by design 2) applies to all mode changes triggered via spi commands table 23 electrical characteristics (cont?d) v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. csn clk sdi sdo 14 13 not defined lsb msb flag lsb msb 16 27 29 19 17 28 24 20 15 18
data sheet 132 rev. 1.1, 2014-10-23 TLE9260QXV33 application information 15 application information 15.1 application diagram note: the following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. figure 47 simplified application diagram c 1 s 1 vbat c 11 r 10 canh c 12 r 11 canl r 2 v ss v dd csn clk sdi sdo c int csn clk sdo sdi fox vcc1 c 4 v cc 1 c 5 wk1 hs1 vs reset int ro vcan gnd v s logic state machine application _inform ation _tle 9260 . vsd v s t1 canh canl can cell vbat vbat vs tle9260 v s hs2 hs3 vshs hs4 lh v cc2 wk3 wk2 r 1 r 4 s 3 r 6 r 5 r 3 hall1 hall2 q1 q2 d 1 c 7 r 8 d 3 other loads , e.g . sensor , opamp , ... c 8 r 7 d 4 txd can rxd can txd can rxd can vcc2 vshs vshs vshs vshs d 2 c 2 c 3 note: the external capacitance on fo 3/test must be <=10nf in oder to ensure proper detection of sbc development mode und sbc user mode operation c 9 c 10 c 6 v cc 2 r 9 c 17 c 18 s 2
data sheet 133 rev. 1.1, 2014-10-23 TLE9260QXV33 application information note: unused outputs are recommended to be left unconnec ted on the application board. if unused output pins are routed to an external connector which leaves the ec u, then these pins should have provision for a zero ohm jumper (depopulated if unused) or esd protection. table 24 bill of material for simplified application diagram ref. typical value purpose / comment capacitances c1 68f buffering capacitor to cut off battery spikes, depending on application c2 100nf emc, blocking capacitor c3 22f buffering capacitor to cut off batter y spikes from vshs as separate supply input; depending on application, only needed if vshs is not connected to vs; c4 2.2f low esr as required by app lication, min. 470nf for stability c5 100nf ceramic spike filter ing, improve stability of supply for microcontroller; not needed for sbc c6 2.2f low esr blocking capacito r, min. 470nf for stability; if used for can supply place a 100nf ceramic capacitor in addition very close to vcan pin for optimum emc behavior c7 33nf as required by application, mandat ory protection for of f-board connections c8 33nf as required by application, mandat ory protection for of f-board connections c17 47pf only required in case of off-board connection to optimize emc behavior, place close to pin c18 47pf only required in case of off-board connection to optimize emc behavior, place close to pin c9 10nf spike filtering, as required by applic ation, mandatory protection for off-board connections (see also simplified app lication diagram with the alternate measurement function) c10 10nf spike filtering, as required by app lication, mandatory protection for off-board connections c11 10nf spike filtering, as required by app lication, mandatory protection for off-board connections c12 4.7nf / oem dependent sp lit termination stability resistances r1 10k ? wetting current of the switch, as required by application r2 10k ? limit the wk pin current, e.g. for iso pulses r3 10k ? wetting current of the switch, as required by application r4 10k ? limit the wk pin current, e.g. for iso pulses r5 10k ? wetting current of the switch, as required by application r6 10k ? limit the wk pin current, e.g. for iso pulses r7 depending on led config. led current li mitation, as required by application r8 depending on led config. led current li mitation, as required by application r9 47k ? selection of hardware configuration 1/ 3, i.e. in case of wd failure sbc restart mode is entered. if not connected, then hardware configuration 2/4 is selected
data sheet 134 rev. 1.1, 2014-10-23 TLE9260QXV33 application information note: this is a simplified example of an application circuit. the function must be verified in the real application. r10 60 ? / oem dependent can bus termination r11 60 ? / oem dependent can bus termination r15 10k ? wk1 pin current limitation, e.g. for iso pulses, for alternate measurement function (see also simplified application diagram with the alternate measurement function) r16 depending on application and microcontroller voltage divider resistor to adjust measurement voltage to microcontroller adc input range (see also simplified application diagram with the alternate measurement function) r17 depending on application and microcontroller voltage divider resistor to adjust measurement voltage to microcontroller adc input range (see also simplified application diagram with the alternate measurement function) active components d1 e.g. bas 3010a, infineon reverse po larity protection for vs supply pins d2 e.g. bas 3010a, infineon reverse polarity protecti on for vshs supply pin; if separate supplies are not needed, then connect vshs to vs pins d3 led as required by application, configure series resistor accordingly d4 led as required by application, configure series resistor accordingly t1 e.g. bcr191w high active fo control c e.g. tc2xxx microcontroller table 24 bill of material for simplified application diagram (cont?d) ref. typical value purpose / comment
data sheet 135 rev. 1.1, 2014-10-23 TLE9260QXV33 application information figure 48 simplified application diagram with the alternate measurement function via wk1 and wk2 note: this is a very simplified example of an applicatio n circuit. the function must be verified in the real application.wk1 must be connected to signal to be measured and wk2 is the output to the microcontroller supervision function. the maximum current into wk 1 must be <500ua. the minimum current into wk1 should be >5ua to ensure proper operation. c 1 e.g. 470uf c 2 v ss v dd csn clk sdi sdo c txd can rxd can int csn clk sdo sdi txd can rxd can vcc1 c 4 v cc1 c 5 wk1 vs reset int ro gnd v s logic state machine vbat vbat vs tle9260 wk2 r 6 adc_x vbat_uc d 1 d 2 10k c 9 10n vbat_uc r 16 r 17 max. 500ua iso pulse protection s 1 note: max. wk1 input current limited to 500a to ensure accuracy and proper operation ;
data sheet 136 rev. 1.1, 2014-10-23 TLE9260QXV33 application information 15.2 esd tests note: tests for esd robustness according to iec61000-4-2 ?gun test? (150pf, 330 ? ) will been performed. the results and test condition w ill be available in a test report. the ta rget values for the test are listed in table 25 below. emc and esd susceptibility tests accord ing to sae j2962-2 (2010) have been pe rformed. tested by external test house (ul llc, test report nr. 2013-474a) table 25 esd ?gun test? performed test r esult unit remarks esd at pin canh, canl, vs, wk1..3, hsx, vcc2 versus gnd >6 kv 1)2) positive pulse 1) esd test ?gun test? is specified with external componen ts for pins vs, wk1..3, hsx and vcc2. see the application diagram in chapter 15.1 for more information. 2) esd susceptibility ?esd gun? according lin emc 1.3 test s pecification, section 4.3 (iec 61000-4-2). tested by external test house (ibee zwickau, emc test report nr. 07-10-13) esd at pin canh, canl, vs, wk1..3, hsx, vcc2 versus gnd < -6 kv 1)2) negative pulse
data sheet 137 rev. 1.1, 2014-10-23 TLE9260QXV33 application information 15.3 thermal behavior of package below figure shows the thermal resistance ( r th_ja ) of the device vs. the cooling area on the bottom of the pcb for ta = 85c. every line reflects a di fferent pcb and thermal via design. figure 49 thermal resistance ( r th_ja ) vs. cooling area
data sheet 138 rev. 1.1, 2014-10-23 TLE9260QXV33 application information figure 50 board setup board setup is defined according to jesd 51-2,-5,-7. board: 76.2x114.3x1.5m m3 with 2 inner copper layers (35m thick), with thermal via array under the exposed pad contacting the first inner copper layer and 300mm 2 cooling area on the bottom layer (70m). pcb (top view) pcb (bottom view) detail solderarea 1 , 5 mm 1 , 5 mm 70m modelled (traces) 35m, 90% metalization* 35m, 90% metalization* 70m / 5% metalization + cooling area *: means percentual cu metalization on each layer cross section (jedec 1s0p) with cooling area cross section (jedec 2s2p) with cooling area
data sheet 139 rev. 1.1, 2014-10-23 TLE9260QXV33 package outlines 16 package outlines figure 51 pg-vqfn-48-31 note: for assembly recommendations please also refer to the documents "recommenda tions for board assembly (vqfn and iqfn)" and "vqfn48 layout hints" on the infineon website ( www.infineon.com ). the pg-vqfn-48-31 package is a leadless exposed pad power package featuring lead tip inspection (lti) to support automatic optical inspection (aoi). green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). pg-vqfn-48-29, -31-po v03 7 0.1 a 6.8 7 0.1 b 11 x 0.5 = 5.5 0.5 0.5 0.07 0.1 0.05 0.15 0.05 (6) (5.2) 0.9 max. (0.65) +0.03 1) 2) 48x 0.08 (0.2) 0.05 max. c (5.2) (6) 0.1 0.03 0.05 0.23 m 48x 0.1 a b c 1) vertical burr 0.03 max., all sides 2) this four metal areas have exposed diepad potential index marking seating plane index marking 6.8 12 1 13 24 25 36 (0.35) 37 48 0.4 x 45 for further info rmation on alternative pa ckages, please visit our website: http://www.infineon.com/packages . dimensions in mm
data sheet 140 rev. 1.1, 2014-10-23 TLE9260QXV33 revision history 17 revision history table 26 revision history revision date changes rev 1.1 2014-10-23 initial release
edition 2014-10-23 published by infineon technologies ag 81726 munich, germany ? 2014 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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